reg_latch.tan.qmsg

是一些很好的FPGA设计实例

{ "Info" "ITAN_NO_REG2REG_EXIST" "CLK " "Info: No valid register-to-register data paths exist for clock \"CLK\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "74175:inst\|13 4D CLK 2.900 ns register " "Info: tsu for register \"74175:inst\|13\" (data pin = \"4D\", clock pin = \"CLK\") is 2.900 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.100 ns + Longest pin register " "Info: + Longest pin to register delay is 3.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.700 ns) 0.700 ns 4D 1 PIN PIN_21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.700 ns) = 0.700 ns; Loc. = PIN_21; Fanout = 1; PIN Node = '4D'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { 4D } "NODE_NAME" } } { "reg_latch.bdf" "" { Schematic "C:/altera/ym/text5/reg_latch.bdf" { { 120 200 368 136 "4D" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(1.500 ns) 3.100 ns 74175:inst\|13 2 REG LC5 2 " "Info: 2: + IC(0.900 ns) + CELL(1.500 ns) = 3.100 ns; Loc. = LC5; Fanout = 2; REG Node = '74175:inst\|13'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { 4D 74175:inst|13 } "NODE_NAME" } } { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 504 352 416 584 "13" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 70.97 % ) " "Info: Total cell delay = 2.200 ns ( 70.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.900 ns ( 29.03 % ) " "Info: Total interconnect delay = 0.900 ns ( 29.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.100 ns" { 4D 74175:inst|13 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.100 ns" { 4D 4D~out 74175:inst|13 } { 0.000ns 0.000ns 0.900ns } { 0.000ns 0.700ns 1.500ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 504 352 416 584 "13" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.500 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 0.900 ns CLK 1 CLK PIN_43 4 " "Info: 1: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "reg_latch.bdf" "" { Schematic "C:/altera/ym/text5/reg_latch.bdf" { { 200 200 368 216 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 1.500 ns 74175:inst\|13 2 REG LC5 2 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.500 ns; Loc. = LC5; Fanout = 2; REG Node = '74175:inst\|13'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.600 ns" { CLK 74175:inst|13 } "NODE_NAME" } } { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 504 352 416 584 "13" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK 74175:inst|13 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { CLK CLK~out 74175:inst|13 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.600ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.100 ns" { 4D 74175:inst|13 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.100 ns" { 4D 4D~out 74175:inst|13 } { 0.000ns 0.000ns 0.900ns } { 0.000ns 0.700ns 1.500ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK 74175:inst|13 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { CLK CLK~out 74175:inst|13 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.600ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK 4QN 74175:inst\|13 6.000 ns register " "Info: tco from clock \"CLK\" to destination pin \"4QN\" through register \"74175:inst\|13\" is 6.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 1.500 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 0.900 ns CLK 1 CLK PIN_43 4 " "Info: 1: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "reg_latch.bdf" "" { Schematic "C:/altera/ym/text5/reg_latch.bdf" { { 200 200 368 216 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 1.500 ns 74175:inst\|13 2 REG LC5 2 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.500 ns; Loc. = LC5; Fanout = 2; REG Node = '74175:inst\|13'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.600 ns" { CLK 74175:inst|13 } "NODE_NAME" } } { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 504 352 416 584 "13" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK 74175:inst|13 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { CLK CLK~out 74175:inst|13 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.600ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.700 ns + " "Info: + Micro clock to output delay of source is 0.700 ns" {  } { { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 504 352 416 584 "13" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.800 ns + Longest register pin " "Info: + Longest register to pin delay is 3.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 74175:inst\|13 1 REG LC5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 2; REG Node = '74175:inst\|13'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { 74175:inst|13 } "NODE_NAME" } } { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 504 352 416 584 "13" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(2.100 ns) 3.000 ns 74175:inst\|13~2 2 COMB LC10 1 " "Info: 2: + IC(0.900 ns) + CELL(2.100 ns) = 3.000 ns; Loc. = LC10; Fanout = 1; COMB Node = '74175:inst\|13~2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.000 ns" { 74175:inst|13 74175:inst|13~2 } "NODE_NAME" } } { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 504 352 416 584 "13" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 3.800 ns 4QN 3 PIN PIN_14 0 " "Info: 3: + IC(0.000 ns) + CELL(0.800 ns) = 3.800 ns; Loc. = PIN_14; Fanout = 0; PIN Node = '4QN'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.800 ns" { 74175:inst|13~2 4QN } "NODE_NAME" } } { "reg_latch.bdf" "" { Schematic "C:/altera/ym/text5/reg_latch.bdf" { { 184 488 664 200 "4QN" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.900 ns ( 76.32 % ) " "Info: Total cell delay = 2.900 ns ( 76.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.900 ns ( 23.68 % ) " "Info: Total interconnect delay = 0.900 ns ( 23.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.800 ns" { 74175:inst|13 74175:inst|13~2 4QN } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.800 ns" { 74175:inst|13 74175:inst|13~2 4QN } { 0.000ns 0.900ns 0.000ns } { 0.000ns 2.100ns 0.800ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK 74175:inst|13 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { CLK CLK~out 74175:inst|13 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.600ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.800 ns" { 74175:inst|13 74175:inst|13~2 4QN } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.800 ns" { 74175:inst|13 74175:inst|13~2 4QN } { 0.000ns 0.900ns 0.000ns } { 0.000ns 2.100ns 0.800ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "74175:inst\|13 4D CLK -1.000 ns register " "Info: th for register \"74175:inst\|13\" (data pin = \"4D\", clock pin = \"CLK\") is -1.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.500 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 0.900 ns CLK 1 CLK PIN_43 4 " "Info: 1: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "reg_latch.bdf" "" { Schematic "C:/altera/ym/text5/reg_latch.bdf" { { 200 200 368 216 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 1.500 ns 74175:inst\|13 2 REG LC5 2 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.500 ns; Loc. = LC5; Fanout = 2; REG Node = '74175:inst\|13'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.600 ns" { CLK 74175:inst|13 } "NODE_NAME" } } { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 504 352 416 584 "13" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK 74175:inst|13 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { CLK CLK~out 74175:inst|13 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.600ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.600 ns + " "Info: + Micro hold delay of destination is 0.600 ns" {  } { { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 504 352 416 584 "13" "" } } } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.100 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.700 ns) 0.700 ns 4D 1 PIN PIN_21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.700 ns) = 0.700 ns; Loc. = PIN_21; Fanout = 1; PIN Node = '4D'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { 4D } "NODE_NAME" } } { "reg_latch.bdf" "" { Schematic "C:/altera/ym/text5/reg_latch.bdf" { { 120 200 368 136 "4D" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(1.500 ns) 3.100 ns 74175:inst\|13 2 REG LC5 2 " "Info: 2: + IC(0.900 ns) + CELL(1.500 ns) = 3.100 ns; Loc. = LC5; Fanout = 2; REG Node = '74175:inst\|13'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { 4D 74175:inst|13 } "NODE_NAME" } } { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 504 352 416 584 "13" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 70.97 % ) " "Info: Total cell delay = 2.200 ns ( 70.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.900 ns ( 29.03 % ) " "Info: Total interconnect delay = 0.900 ns ( 29.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.100 ns" { 4D 74175:inst|13 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.100 ns" { 4D 4D~out 74175:inst|13 } { 0.000ns 0.000ns 0.900ns } { 0.000ns 0.700ns 1.500ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK 74175:inst|13 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { CLK CLK~out 74175:inst|13 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.600ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.100 ns" { 4D 74175:inst|13 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.100 ns" { 4D 4D~out 74175:inst|13 } { 0.000ns 0.000ns 0.900ns } { 0.000ns 0.700ns 1.500ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jan 26 16:30:39 2007 " "Info: Processing ended: Fri Jan 26 16:30:39 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}