reg_latch.hier_info

是一些很好的FPGA设计实例

|reg_latch
1Q <= 74175:inst.1Q
CLRN => 74175:inst.CLRN
CLK => 74175:inst.CLK
3D => 74175:inst.3D
2D => 74175:inst.2D
1D => 74175:inst.1D
4D => 74175:inst.4D
1QN <= 74175:inst.1QN
2Q <= 74175:inst.2Q
2QN <= 74175:inst.2QN
3Q <= 74175:inst.3Q
3QN <= 74175:inst.3QN
4Q <= 74175:inst.4Q
4QN <= 74175:inst.4QN


|reg_latch|74175:inst
1Q <= 16.DB_MAX_OUTPUT_PORT_TYPE
CLRN => 16.ACLR
CLRN => 15.ACLR
CLRN => 14.ACLR
CLRN => 13.ACLR
CLK => 16.CLK
CLK => 15.CLK
CLK => 14.CLK
CLK => 13.CLK
1D => 16.DATAIN
1QN <= 1.DB_MAX_OUTPUT_PORT_TYPE
2Q <= 15.DB_MAX_OUTPUT_PORT_TYPE
2D => 15.DATAIN
2QN <= 2.DB_MAX_OUTPUT_PORT_TYPE
3Q <= 14.DB_MAX_OUTPUT_PORT_TYPE
3D => 14.DATAIN
3QN <= 3.DB_MAX_OUTPUT_PORT_TYPE
4Q <= 13.DB_MAX_OUTPUT_PORT_TYPE
4D => 13.DATAIN
4QN <= 4.DB_MAX_OUTPUT_PORT_TYPE