ff.tan.rpt

是一些很好的FPGA设计实例

; N/A   ; None         ; 4.100 ns   ; R    ; inst    ; CLK      ;
; N/A   ; None         ; 4.100 ns   ; R    ; inst~9  ; CLK      ;
+-------+--------------+------------+------+---------+----------+


+-----------------------------------------------------------------+
; tco                                                             ;
+-------+--------------+------------+---------+------+------------+
; Slack ; Required tco ; Actual tco ; From    ; To   ; From Clock ;
+-------+--------------+------------+---------+------+------------+
; N/A   ; None         ; 8.300 ns   ; inst~9  ; SRNQ ; CLK        ;
; N/A   ; None         ; 8.300 ns   ; inst    ; SRQ  ; CLK        ;
; N/A   ; None         ; 7.800 ns   ; inst2~3 ; TNQ  ; CLK        ;
; N/A   ; None         ; 7.800 ns   ; inst2   ; TQ   ; CLK        ;
; N/A   ; None         ; 7.700 ns   ; inst3~2 ; DNQ  ; CLK        ;
; N/A   ; None         ; 7.700 ns   ; inst3   ; DQ   ; CLK        ;
; N/A   ; None         ; 7.600 ns   ; inst1~9 ; JKNQ ; CLK        ;
; N/A   ; None         ; 7.600 ns   ; inst1   ; JKQ  ; CLK        ;
+-------+--------------+------------+---------+------+------------+


+---------------------------------------------------------------------+
; th                                                                  ;
+---------------+-------------+-----------+------+---------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To      ; To Clock ;
+---------------+-------------+-----------+------+---------+----------+
; N/A           ; None        ; -2.500 ns ; R    ; inst    ; CLK      ;
; N/A           ; None        ; -2.500 ns ; R    ; inst~9  ; CLK      ;
; N/A           ; None        ; -2.700 ns ; S    ; inst    ; CLK      ;
; N/A           ; None        ; -2.700 ns ; S    ; inst~9  ; CLK      ;
; N/A           ; None        ; -2.800 ns ; D    ; inst3   ; CLK      ;
; N/A           ; None        ; -2.800 ns ; D    ; inst3~2 ; CLK      ;
; N/A           ; None        ; -2.800 ns ; K    ; inst1   ; CLK      ;
; N/A           ; None        ; -2.800 ns ; K    ; inst1~9 ; CLK      ;
; N/A           ; None        ; -3.200 ns ; T    ; inst2   ; CLK      ;
; N/A           ; None        ; -3.200 ns ; T    ; inst2~3 ; CLK      ;
; N/A           ; None        ; -3.800 ns ; J    ; inst1   ; CLK      ;
; N/A           ; None        ; -3.800 ns ; J    ; inst1~9 ; CLK      ;
+---------------+-------------+-----------+------+---------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Fri Feb 09 02:12:45 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off FF -c FF
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" Internal fmax is restricted to 200.0 MHz between source register "inst" and destination register "inst"
    Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.900 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_F26; Fanout = 3; REG Node = 'inst'
            Info: 2: + IC(0.200 ns) + CELL(0.700 ns) = 0.900 ns; Loc. = LC4_F26; Fanout = 3; REG Node = 'inst'
            Info: Total cell delay = 0.700 ns ( 77.78 % )
            Info: Total interconnect delay = 0.200 ns ( 22.22 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK" to destination register is 1.800 ns
                Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 8; CLK Node = 'CLK'
                Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC4_F26; Fanout = 3; REG Node = 'inst'
                Info: Total cell delay = 1.500 ns ( 83.33 % )
                Info: Total interconnect delay = 0.300 ns ( 16.67 % )
            Info: - Longest clock path from clock "CLK" to source register is 1.800 ns
                Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 8; CLK Node = 'CLK'
                Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC4_F26; Fanout = 3; REG Node = 'inst'
                Info: Total cell delay = 1.500 ns ( 83.33 % )
                Info: Total interconnect delay = 0.300 ns ( 16.67 % )
        Info: + Micro clock to output delay of source is 0.400 ns
        Info: + Micro setup delay of destination is 0.600 ns
Info: tsu for register "inst1" (data pin = "J", clock pin = "CLK") is 5.400 ns
    Info: + Longest pin to register delay is 6.600 ns
        Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_47; Fanout = 2; PIN Node = 'J'
        Info: 2: + IC(2.400 ns) + CELL(0.700 ns) = 6.600 ns; Loc. = LC1_D34; Fanout = 3; REG Node = 'inst1'
        Info: Total cell delay = 4.200 ns ( 63.64 % )
        Info: Total interconnect delay = 2.400 ns ( 36.36 % )
    Info: + Micro setup delay of destination is 0.600 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 1.800 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 8; CLK Node = 'CLK'
        Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC1_D34; Fanout = 3; REG Node = 'inst1'
        Info: Total cell delay = 1.500 ns ( 83.33 % )
        Info: Total interconnect delay = 0.300 ns ( 16.67 % )
Info: tco from clock "CLK" to destination pin "SRNQ" through register "inst~9" is 8.300 ns
    Info: + Longest clock path from clock "CLK" to source register is 1.800 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 8; CLK Node = 'CLK'
        Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC7_F26; Fanout = 1; REG Node = 'inst~9'
        Info: Total cell delay = 1.500 ns ( 83.33 % )
        Info: Total interconnect delay = 0.300 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 0.400 ns
    Info: + Longest register to pin delay is 6.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_F26; Fanout = 1; REG Node = 'inst~9'
        Info: 2: + IC(1.500 ns) + CELL(4.600 ns) = 6.100 ns; Loc. = PIN_24; Fanout = 0; PIN Node = 'SRNQ'
        Info: Total cell delay = 4.600 ns ( 75.41 % )
        Info: Total interconnect delay = 1.500 ns ( 24.59 % )
Info: th for register "inst" (data pin = "R", clock pin = "CLK") is -2.500 ns
    Info: + Longest clock path from clock "CLK" to destination register is 1.800 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 8; CLK Node = 'CLK'
        Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC4_F26; Fanout = 3; REG Node = 'inst'
        Info: Total cell delay = 1.500 ns ( 83.33 % )
        Info: Total interconnect delay = 0.300 ns ( 16.67 % )
    Info: + Micro hold delay of destination is 1.000 ns
    Info: - Shortest pin to register delay is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_46; Fanout = 2; PIN Node = 'R'
        Info: 2: + IC(1.300 ns) + CELL(0.500 ns) = 5.300 ns; Loc. = LC4_F26; Fanout = 3; REG Node = 'inst'
        Info: Total cell delay = 4.000 ns ( 75.47 % )
        Info: Total interconnect delay = 1.300 ns ( 24.53 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Feb 09 02:12:46 2007
    Info: Elapsed time: 00:00:02