bk_mux.map.qmsg

是一些很好的FPGA设计实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jan 20 03:00:40 2007 " "Info: Processing started: Sat Jan 20 03:00:40 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off bk_mux -c bk_mux " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off bk_mux -c bk_mux" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bk_mux.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file bk_mux.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 bk_mux " "Info: Found entity 1: bk_mux" {  } { { "bk_mux.bdf" "" { Schematic "C:/altera/ym/text6/bk_mux.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "bk_mux " "Info: Elaborating entity \"bk_mux\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "GN 74151 inst " "Warning: Port \"GN\" of type 74151 and instance \"inst\" is missing source signal" {  } { { "bk_mux.bdf" "" { Schematic "C:/altera/ym/text6/bk_mux.bdf" { { 32 296 416 256 "inst" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D7 74151 inst " "Warning: Port \"D7\" of type 74151 and instance \"inst\" is missing source signal" {  } { { "bk_mux.bdf" "" { Schematic "C:/altera/ym/text6/bk_mux.bdf" { { 32 296 416 256 "inst" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../quartus60/libraries/others/maxplus2/74151.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../quartus60/libraries/others/maxplus2/74151.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 74151 " "Info: Found entity 1: 74151" {  } { { "74151.tdf" "" { Text "c:/altera/quartus60/libraries/others/maxplus2/74151.tdf" 11 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74151 74151:inst " "Info: Elaborating entity \"74151\" for hierarchy \"74151:inst\"" {  } { { "bk_mux.bdf" "inst" { Schematic "C:/altera/ym/text6/bk_mux.bdf" { { 32 296 416 256 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "74151:inst " "Info: Elaborated megafunction instantiation \"74151:inst\"" {  } { { "bk_mux.bdf" "" { Schematic "C:/altera/ym/text6/bk_mux.bdf" { { 32 296 416 256 "inst" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../quartus60/libraries/others/maxplus2/f74151.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../quartus60/libraries/others/maxplus2/f74151.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 f74151 " "Info: Found entity 1: f74151" {  } { { "f74151.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/f74151.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "f74151 74151:inst\|f74151:sub " "Info: Elaborating entity \"f74151\" for hierarchy \"74151:inst\|f74151:sub\"" {  } { { "74151.tdf" "sub" { Text "c:/altera/quartus60/libraries/others/maxplus2/74151.tdf" 24 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "74151:inst\|f74151:sub 74151:inst " "Info: Elaborated megafunction instantiation \"74151:inst\|f74151:sub\", which is child of megafunction instantiation \"74151:inst\"" {  } { { "74151.tdf" "" { Text "c:/altera/quartus60/libraries/others/maxplus2/74151.tdf" 24 3 0 } } { "bk_mux.bdf" "" { Schematic "C:/altera/ym/text6/bk_mux.bdf" { { 32 296 416 256 "inst" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "4_2counter.bdf 1 1 " "Warning: Using design file 4_2counter.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 4_2counter " "Info: Found entity 1: 4_2counter" {  } { { "4_2counter.bdf" "" { Schematic "C:/altera/ym/text6/4_2counter.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "4_2counter 4_2counter:inst9 " "Info: Elaborating entity \"4_2counter\" for hierarchy \"4_2counter:inst9\"" {  } { { "bk_mux.bdf" "inst9" { Schematic "C:/altera/ym/text6/bk_mux.bdf" { { 24 24 120 152 "inst9" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WFTM_CASCADE_NON_COMB_IN" "74151:inst\|f74151:sub\|75 " "Warning: CASCADE primitive \"74151:inst\|f74151:sub\|75\" is fed by non-combinational logic" {  } { { "f74151.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/f74151.bdf" { { 128 560 616 160 "75" "" } } } }  } 0 0 "CASCADE primitive \"%1!s!\" is fed by non-combinational logic" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "9 " "Info: Implemented 9 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "7 " "Info: Implemented 7 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jan 20 03:00:41 2007 " "Info: Processing ended: Sat Jan 20 03:00:41 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}