📄 bk_mux.tan.rpt
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Timing Analyzer report for bk_mux
Sat Jan 20 03:00:49 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tco
7. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+------------------------+------------------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+------------------------+------------------------+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 12.200 ns ; 4_2counter:inst9|inst1 ; y ; clk ; -- ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; 4_2counter:inst9|inst1 ; 4_2counter:inst9|inst1 ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+------------------------+------------------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1K30QC208-2 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+------------------------+------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+------------------------+------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; 4_2counter:inst9|inst ; 4_2counter:inst9|inst ; clk ; clk ; None ; None ; 0.700 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; 4_2counter:inst9|inst2 ; 4_2counter:inst9|inst2 ; clk ; clk ; None ; None ; 0.700 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; 4_2counter:inst9|inst1 ; 4_2counter:inst9|inst1 ; clk ; clk ; None ; None ; 0.700 ns ;
+-------+------------------------------------------------+------------------------+------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+------------------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+------------------------+----+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+------------------------+----+------------+
; N/A ; None ; 12.200 ns ; 4_2counter:inst9|inst1 ; y ; clk ;
; N/A ; None ; 10.900 ns ; 4_2counter:inst9|inst2 ; y ; clk ;
; N/A ; None ; 10.800 ns ; 4_2counter:inst9|inst ; y ; clk ;
+-------+--------------+------------+------------------------+----+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Sat Jan 20 03:00:49 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off bk_mux -c bk_mux
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected ripple clock "4_2counter:inst9|inst1" as buffer
Info: Detected ripple clock "4_2counter:inst9|inst" as buffer
Info: Clock "clk" Internal fmax is restricted to 200.0 MHz between source register "4_2counter:inst9|inst" and destination register "4_2counter:inst9|inst"
Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 0.700 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_C24; Fanout = 5; REG Node = '4_2counter:inst9|inst'
Info: 2: + IC(0.200 ns) + CELL(0.500 ns) = 0.700 ns; Loc. = LC1_C24; Fanout = 5; REG Node = '4_2counter:inst9|inst'
Info: Total cell delay = 0.500 ns ( 71.43 % )
Info: Total interconnect delay = 0.200 ns ( 28.57 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 1.800 ns
Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC1_C24; Fanout = 5; REG Node = '4_2counter:inst9|inst'
Info: Total cell delay = 1.500 ns ( 83.33 % )
Info: Total interconnect delay = 0.300 ns ( 16.67 % )
Info: - Longest clock path from clock "clk" to source register is 1.800 ns
Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC1_C24; Fanout = 5; REG Node = '4_2counter:inst9|inst'
Info: Total cell delay = 1.500 ns ( 83.33 % )
Info: Total interconnect delay = 0.300 ns ( 16.67 % )
Info: + Micro clock to output delay of source is 0.400 ns
Info: + Micro setup delay of destination is 0.600 ns
Info: tco from clock "clk" to destination pin "y" through register "4_2counter:inst9|inst1" is 12.200 ns
Info: + Longest clock path from clock "clk" to source register is 3.100 ns
Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(0.300 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC1_C24; Fanout = 5; REG Node = '4_2counter:inst9|inst'
Info: 3: + IC(0.900 ns) + CELL(0.000 ns) = 3.100 ns; Loc. = LC3_C29; Fanout = 6; REG Node = '4_2counter:inst9|inst1'
Info: Total cell delay = 1.900 ns ( 61.29 % )
Info: Total interconnect delay = 1.200 ns ( 38.71 % )
Info: + Micro clock to output delay of source is 0.400 ns
Info: + Longest register to pin delay is 8.700 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_C29; Fanout = 6; REG Node = '4_2counter:inst9|inst1'
Info: 2: + IC(0.200 ns) + CELL(0.500 ns) = 0.700 ns; Loc. = LC6_C29; Fanout = 1; COMB Node = '74151:inst|f74151:sub|75~10'
Info: 3: + IC(0.000 ns) + CELL(1.200 ns) = 1.900 ns; Loc. = LC7_C29; Fanout = 1; COMB Node = '74151:inst|f74151:sub|78~3'
Info: 4: + IC(0.200 ns) + CELL(1.100 ns) = 3.200 ns; Loc. = LC4_C29; Fanout = 1; COMB Node = '74151:inst|f74151:sub|81~4'
Info: 5: + IC(0.900 ns) + CELL(4.600 ns) = 8.700 ns; Loc. = PIN_19; Fanout = 0; PIN Node = 'y'
Info: Total cell delay = 7.400 ns ( 85.06 % )
Info: Total interconnect delay = 1.300 ns ( 14.94 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
Info: Processing ended: Sat Jan 20 03:00:49 2007
Info: Elapsed time: 00:00:01
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