epasswordlock.tan.rpt

是一些很好的FPGA设计实例

+------------------------------+------------------------------------------+---------------+------------------------------------------------+---------------------------------------------------+----------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Type                         ; Slack                                    ; Required Time ; Actual Time                                    ; From                                              ; To                                                                                                 ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+---------------------------------------------------+----------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A                                      ; None          ; 4.700 ns                                       ; lie[3]                                            ; keyboard:inst|CONTROL1:inst3|inst2                                                                 ; --         ; clk1     ; 0            ;
; Worst-case tco               ; N/A                                      ; None          ; 32.000 ns                                      ; keyboard:inst|7493:inst5|15                       ; OD                                                                                                 ; clk1       ; --       ; 0            ;
; Worst-case tpd               ; N/A                                      ; None          ; 12.400 ns                                      ; lie[3]                                            ; signal                                                                                             ; --         ; --       ; 0            ;
; Worst-case th                ; N/A                                      ; None          ; 8.700 ns                                       ; lie[3]                                            ; keyboard:inst|KEYVALUE:inst1|dout[1]                                                               ; --         ; clk1     ; 0            ;
; Clock Setup: 'clk1'          ; N/A                                      ; None          ; 33.56 MHz ( period = 29.800 ns )               ; keyboard:inst|KEYVALUE:inst1|dout[3]              ; keyboard:inst|CONTROL1:inst3|control:inst|lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[31] ; clk1       ; clk1     ; 0            ;
; Clock Setup: 'clk'           ; N/A                                      ; None          ; 116.28 MHz ( period = 8.600 ns )               ; keyboard:inst|COUNT:inst|7493:inst1|15            ; keyboard:inst|KEYVALUE:inst1|dout[3]                                                               ; clk        ; clk      ; 0            ;
; Clock Setup: 'lie[3]'        ; N/A                                      ; None          ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; keyboard:inst|COUNT:inst|7493:inst1|16            ; keyboard:inst|COUNT:inst|7493:inst1|16                                                             ; lie[3]     ; lie[3]   ; 0            ;
; Clock Setup: 'lie[2]'        ; N/A                                      ; None          ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; keyboard:inst|COUNT:inst|7493:inst1|16            ; keyboard:inst|COUNT:inst|7493:inst1|16                                                             ; lie[2]     ; lie[2]   ; 0            ;
; Clock Setup: 'lie[1]'        ; N/A                                      ; None          ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; keyboard:inst|COUNT:inst|7493:inst1|16            ; keyboard:inst|COUNT:inst|7493:inst1|16                                                             ; lie[1]     ; lie[1]   ; 0            ;
; Clock Setup: 'lie[0]'        ; N/A                                      ; None          ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; keyboard:inst|COUNT:inst|7493:inst1|16            ; keyboard:inst|COUNT:inst|7493:inst1|16                                                             ; lie[0]     ; lie[0]   ; 0            ;
; Clock Hold: 'clk1'           ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; keyboard:inst|CONTROL1:inst3|control:inst|DATA[9] ; keyboard:inst|smdisplay:inst4|74175:inst12|15                                                      ; clk1       ; clk1     ; 83           ;
; Total number of failed paths ;                                          ;               ;                                                ;                                                   ;                                                                                                    ;            ;          ; 83           ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+---------------------------------------------------+----------------------------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1K30QC208-2      ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;