tellpw.hier_info

是一些很好的FPGA设计实例

|tellpw
DIN[0] => Equal0.IN23
DIN[1] => Equal0.IN22
DIN[2] => Equal0.IN21
DIN[3] => Equal0.IN20
DIN[4] => Equal0.IN19
DIN[5] => Equal0.IN18
DIN[6] => Equal0.IN17
DIN[7] => Equal0.IN16
DIN[8] => Equal0.IN15
DIN[9] => Equal0.IN14
DIN[10] => Equal0.IN13
DIN[11] => Equal0.IN12
DIN[12] => Equal0.IN11
DIN[13] => Equal0.IN10
DIN[14] => Equal0.IN9
DIN[15] => Equal0.IN8
DIN[16] => Equal0.IN7
DIN[17] => Equal0.IN6
DIN[18] => Equal0.IN5
DIN[19] => Equal0.IN4
DIN[20] => Equal0.IN3
DIN[21] => Equal0.IN2
DIN[22] => Equal0.IN1
DIN[23] => Equal0.IN0
DATA[0] => Equal0.IN47
DATA[1] => Equal0.IN46
DATA[2] => Equal0.IN45
DATA[3] => Equal0.IN44
DATA[4] => Equal0.IN43
DATA[5] => Equal0.IN42
DATA[6] => Equal0.IN41
DATA[7] => Equal0.IN40
DATA[8] => Equal0.IN39
DATA[9] => Equal0.IN38
DATA[10] => Equal0.IN37
DATA[11] => Equal0.IN36
DATA[12] => Equal0.IN35
DATA[13] => Equal0.IN34
DATA[14] => Equal0.IN33
DATA[15] => Equal0.IN32
DATA[16] => Equal0.IN31
DATA[17] => Equal0.IN30
DATA[18] => Equal0.IN29
DATA[19] => Equal0.IN28
DATA[20] => Equal0.IN27
DATA[21] => Equal0.IN26
DATA[22] => Equal0.IN25
DATA[23] => Equal0.IN24
cfm => n[0]~reg0.CLK
cfm => lock~reg0.CLK
cfm => ok~reg0.CLK
cfm => n[1]~reg0.CLK
ok <= ok~reg0.DB_MAX_OUTPUT_PORT_TYPE
n[0] <= n[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
n[1] <= n[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lock <= lock~reg0.DB_MAX_OUTPUT_PORT_TYPE