tellpw.tan.qmsg

是一些很好的FPGA设计实例

{ "Info" "ITDB_FULL_TCO_RESULT" "cfm ok ok~reg0 8.700 ns register " "Info: tco from clock \"cfm\" to destination pin \"ok\" through register \"ok~reg0\" is 8.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cfm source 1.800 ns + Longest register " "Info: + Longest clock path from clock \"cfm\" to source register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns cfm 1 CLK PIN_79 4 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'cfm'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cfm } "NODE_NAME" } } { "tellpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/tellpw/tellpw.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.000 ns) 1.800 ns ok~reg0 2 REG LC5_D8 1 " "Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC5_D8; Fanout = 1; REG Node = 'ok~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { cfm ok~reg0 } "NODE_NAME" } } { "tellpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/tellpw/tellpw.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 83.33 % ) " "Info: Total cell delay = 1.500 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.300 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { cfm ok~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { cfm cfm~out ok~reg0 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.400 ns + " "Info: + Micro clock to output delay of source is 0.400 ns" {  } { { "tellpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/tellpw/tellpw.v" 29 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.500 ns + Longest register pin " "Info: + Longest register to pin delay is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ok~reg0 1 REG LC5_D8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_D8; Fanout = 1; REG Node = 'ok~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ok~reg0 } "NODE_NAME" } } { "tellpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/tellpw/tellpw.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(4.600 ns) 6.500 ns ok 2 PIN PIN_29 0 " "Info: 2: + IC(1.900 ns) + CELL(4.600 ns) = 6.500 ns; Loc. = PIN_29; Fanout = 0; PIN Node = 'ok'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.500 ns" { ok~reg0 ok } "NODE_NAME" } } { "tellpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/tellpw/tellpw.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.600 ns ( 70.77 % ) " "Info: Total cell delay = 4.600 ns ( 70.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.900 ns ( 29.23 % ) " "Info: Total interconnect delay = 1.900 ns ( 29.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.500 ns" { ok~reg0 ok } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.500 ns" { ok~reg0 ok } { 0.000ns 1.900ns } { 0.000ns 4.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { cfm ok~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { cfm cfm~out ok~reg0 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.500 ns" { ok~reg0 ok } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.500 ns" { ok~reg0 ok } { 0.000ns 1.900ns } { 0.000ns 4.600ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "ok~reg0 DATA\[8\] cfm -0.500 ns register " "Info: th for register \"ok~reg0\" (data pin = \"DATA\[8\]\", clock pin = \"cfm\") is -0.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cfm destination 1.800 ns + Longest register " "Info: + Longest clock path from clock \"cfm\" to destination register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns cfm 1 CLK PIN_79 4 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'cfm'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cfm } "NODE_NAME" } } { "tellpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/tellpw/tellpw.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.000 ns) 1.800 ns ok~reg0 2 REG LC5_D8 1 " "Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC5_D8; Fanout = 1; REG Node = 'ok~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { cfm ok~reg0 } "NODE_NAME" } } { "tellpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/tellpw/tellpw.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 83.33 % ) " "Info: Total cell delay = 1.500 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.300 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { cfm ok~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { cfm cfm~out ok~reg0 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.000 ns + " "Info: + Micro hold delay of destination is 1.000 ns" {  } { { "tellpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/tellpw/tellpw.v" 29 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.300 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns DATA\[8\] 1 PIN PIN_184 1 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_184; Fanout = 1; PIN Node = 'DATA\[8\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA[8] } "NODE_NAME" } } { "tellpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/tellpw/tellpw.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.900 ns) 2.600 ns Equal0~294 2 COMB LC3_D8 2 " "Info: 2: + IC(0.200 ns) + CELL(0.900 ns) = 2.600 ns; Loc. = LC3_D8; Fanout = 2; COMB Node = 'Equal0~294'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.100 ns" { DATA[8] Equal0~294 } "NODE_NAME" } } { "tellpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/tellpw/tellpw.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.500 ns) 3.300 ns ok~reg0 3 REG LC5_D8 1 " "Info: 3: + IC(0.200 ns) + CELL(0.500 ns) = 3.300 ns; Loc. = LC5_D8; Fanout = 1; REG Node = 'ok~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.700 ns" { Equal0~294 ok~reg0 } "NODE_NAME" } } { "tellpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/tellpw/tellpw.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.900 ns ( 87.88 % ) " "Info: Total cell delay = 2.900 ns ( 87.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 12.12 % ) " "Info: Total interconnect delay = 0.400 ns ( 12.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.300 ns" { DATA[8] Equal0~294 ok~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.300 ns" { DATA[8] DATA[8]~out Equal0~294 ok~reg0 } { 0.000ns 0.000ns 0.200ns 0.200ns } { 0.000ns 1.500ns 0.900ns 0.500ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { cfm ok~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { cfm cfm~out ok~reg0 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.300 ns" { DATA[8] Equal0~294 ok~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.300 ns" { DATA[8] DATA[8]~out Equal0~294 ok~reg0 } { 0.000ns 0.000ns 0.200ns 0.200ns } { 0.000ns 1.500ns 0.900ns 0.500ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 28 04:37:59 2007 " "Info: Processing ended: Wed Feb 28 04:37:59 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}