tellpw.tan.qmsg

是一些很好的FPGA设计实例

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "cfm " "Info: Assuming node \"cfm\" is an undefined clock" {  } { { "tellpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/tellpw/tellpw.v" 3 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cfm" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "cfm register register n\[1\]~reg0 n\[1\]~reg0 200.0 MHz Internal " "Info: Clock \"cfm\" Internal fmax is restricted to 200.0 MHz between source register \"n\[1\]~reg0\" and destination register \"n\[1\]~reg0\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.900 ns + Longest register register " "Info: + Longest register to register delay is 0.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns n\[1\]~reg0 1 REG LC2_D8 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_D8; Fanout = 3; REG Node = 'n\[1\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { n[1]~reg0 } "NODE_NAME" } } { "tellpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/tellpw/tellpw.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.700 ns) 0.900 ns n\[1\]~reg0 2 REG LC2_D8 3 " "Info: 2: + IC(0.200 ns) + CELL(0.700 ns) = 0.900 ns; Loc. = LC2_D8; Fanout = 3; REG Node = 'n\[1\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { n[1]~reg0 n[1]~reg0 } "NODE_NAME" } } { "tellpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/tellpw/tellpw.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.700 ns ( 77.78 % ) " "Info: Total cell delay = 0.700 ns ( 77.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns ( 22.22 % ) " "Info: Total interconnect delay = 0.200 ns ( 22.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { n[1]~reg0 n[1]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "0.900 ns" { n[1]~reg0 n[1]~reg0 } { 0.000ns 0.200ns } { 0.000ns 0.700ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cfm destination 1.800 ns + Shortest register " "Info: + Shortest clock path from clock \"cfm\" to destination register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns cfm 1 CLK PIN_79 4 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'cfm'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cfm } "NODE_NAME" } } { "tellpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/tellpw/tellpw.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.000 ns) 1.800 ns n\[1\]~reg0 2 REG LC2_D8 3 " "Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC2_D8; Fanout = 3; REG Node = 'n\[1\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { cfm n[1]~reg0 } "NODE_NAME" } } { "tellpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/tellpw/tellpw.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 83.33 % ) " "Info: Total cell delay = 1.500 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.300 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { cfm n[1]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { cfm cfm~out n[1]~reg0 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cfm source 1.800 ns - Longest register " "Info: - Longest clock path from clock \"cfm\" to source register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns cfm 1 CLK PIN_79 4 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'cfm'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cfm } "NODE_NAME" } } { "tellpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/tellpw/tellpw.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.000 ns) 1.800 ns n\[1\]~reg0 2 REG LC2_D8 3 " "Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC2_D8; Fanout = 3; REG Node = 'n\[1\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { cfm n[1]~reg0 } "NODE_NAME" } } { "tellpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/tellpw/tellpw.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 83.33 % ) " "Info: Total cell delay = 1.500 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.300 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { cfm n[1]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { cfm cfm~out n[1]~reg0 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { cfm n[1]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { cfm cfm~out n[1]~reg0 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { cfm n[1]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { cfm cfm~out n[1]~reg0 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.400 ns + " "Info: + Micro clock to output delay of source is 0.400 ns" {  } { { "tellpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/tellpw/tellpw.v" 29 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "tellpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/tellpw/tellpw.v" 29 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { n[1]~reg0 n[1]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "0.900 ns" { n[1]~reg0 n[1]~reg0 } { 0.000ns 0.200ns } { 0.000ns 0.700ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { cfm n[1]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { cfm cfm~out n[1]~reg0 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { cfm n[1]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { cfm cfm~out n[1]~reg0 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { n[1]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { n[1]~reg0 } {  } {  } } } { "tellpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/tellpw/tellpw.v" 29 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "lock~reg0 DATA\[15\] cfm 13.600 ns register " "Info: tsu for register \"lock~reg0\" (data pin = \"DATA\[15\]\", clock pin = \"cfm\") is 13.600 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.800 ns + Longest pin register " "Info: + Longest pin to register delay is 14.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns DATA\[15\] 1 PIN PIN_122 1 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_122; Fanout = 1; PIN Node = 'DATA\[15\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA[15] } "NODE_NAME" } } { "tellpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/tellpw/tellpw.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(0.700 ns) 6.400 ns Equal0~350 2 COMB LC7_E24 1 " "Info: 2: + IC(2.200 ns) + CELL(0.700 ns) = 6.400 ns; Loc. = LC7_E24; Fanout = 1; COMB Node = 'Equal0~350'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.900 ns" { DATA[15] Equal0~350 } "NODE_NAME" } } { "tellpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/tellpw/tellpw.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 7.600 ns Equal0~331 3 COMB LC8_E24 1 " "Info: 3: + IC(0.000 ns) + CELL(1.200 ns) = 7.600 ns; Loc. = LC8_E24; Fanout = 1; COMB Node = 'Equal0~331'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.200 ns" { Equal0~350 Equal0~331 } "NODE_NAME" } } { "tellpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/tellpw/tellpw.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(1.100 ns) 10.200 ns Equal0~301 4 COMB LC5_B25 2 " "Info: 4: + IC(1.500 ns) + CELL(1.100 ns) = 10.200 ns; Loc. = LC5_B25; Fanout = 2; COMB Node = 'Equal0~301'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.600 ns" { Equal0~331 Equal0~301 } "NODE_NAME" } } { "tellpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/tellpw/tellpw.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(1.200 ns) 13.800 ns Equal0~302 5 COMB LC6_D8 3 " "Info: 5: + IC(2.400 ns) + CELL(1.200 ns) = 13.800 ns; Loc. = LC6_D8; Fanout = 3; COMB Node = 'Equal0~302'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.600 ns" { Equal0~301 Equal0~302 } "NODE_NAME" } } { "tellpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/tellpw/tellpw.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.800 ns) 14.800 ns lock~reg0 6 REG LC1_D8 2 " "Info: 6: + IC(0.200 ns) + CELL(0.800 ns) = 14.800 ns; Loc. = LC1_D8; Fanout = 2; REG Node = 'lock~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.000 ns" { Equal0~302 lock~reg0 } "NODE_NAME" } } { "tellpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/tellpw/tellpw.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.500 ns ( 57.43 % ) " "Info: Total cell delay = 8.500 ns ( 57.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.300 ns ( 42.57 % ) " "Info: Total interconnect delay = 6.300 ns ( 42.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.800 ns" { DATA[15] Equal0~350 Equal0~331 Equal0~301 Equal0~302 lock~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "14.800 ns" { DATA[15] DATA[15]~out Equal0~350 Equal0~331 Equal0~301 Equal0~302 lock~reg0 } { 0.000ns 0.000ns 2.200ns 0.000ns 1.500ns 2.400ns 0.200ns } { 0.000ns 3.500ns 0.700ns 1.200ns 1.100ns 1.200ns 0.800ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "tellpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/tellpw/tellpw.v" 29 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cfm destination 1.800 ns - Shortest register " "Info: - Shortest clock path from clock \"cfm\" to destination register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns cfm 1 CLK PIN_79 4 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'cfm'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cfm } "NODE_NAME" } } { "tellpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/tellpw/tellpw.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.000 ns) 1.800 ns lock~reg0 2 REG LC1_D8 2 " "Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC1_D8; Fanout = 2; REG Node = 'lock~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { cfm lock~reg0 } "NODE_NAME" } } { "tellpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/tellpw/tellpw.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 83.33 % ) " "Info: Total cell delay = 1.500 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.300 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { cfm lock~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { cfm cfm~out lock~reg0 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.800 ns" { DATA[15] Equal0~350 Equal0~331 Equal0~301 Equal0~302 lock~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "14.800 ns" { DATA[15] DATA[15]~out Equal0~350 Equal0~331 Equal0~301 Equal0~302 lock~reg0 } { 0.000ns 0.000ns 2.200ns 0.000ns 1.500ns 2.400ns 0.200ns } { 0.000ns 3.500ns 0.700ns 1.200ns 1.100ns 1.200ns 0.800ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { cfm lock~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { cfm cfm~out lock~reg0 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}