epasswordlock.tan.qmsg

是一些很好的FPGA设计实例

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "lie\[0\] register register keyboard:inst\|COUNT:inst\|7493:inst1\|15 keyboard:inst\|COUNT:inst\|7493:inst1\|15 200.0 MHz Internal " "Info: Clock \"lie\[0\]\" Internal fmax is restricted to 200.0 MHz between source register \"keyboard:inst\|COUNT:inst\|7493:inst1\|15\" and destination register \"keyboard:inst\|COUNT:inst\|7493:inst1\|15\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.700 ns + Longest register register " "Info: + Longest register to register delay is 0.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns keyboard:inst\|COUNT:inst\|7493:inst1\|15 1 REG LC1_E27 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_E27; Fanout = 6; REG Node = 'keyboard:inst\|COUNT:inst\|7493:inst1\|15'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { keyboard:inst|COUNT:inst|7493:inst1|15 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.500 ns) 0.700 ns keyboard:inst\|COUNT:inst\|7493:inst1\|15 2 REG LC1_E27 6 " "Info: 2: + IC(0.200 ns) + CELL(0.500 ns) = 0.700 ns; Loc. = LC1_E27; Fanout = 6; REG Node = 'keyboard:inst\|COUNT:inst\|7493:inst1\|15'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.700 ns" { keyboard:inst|COUNT:inst|7493:inst1|15 keyboard:inst|COUNT:inst|7493:inst1|15 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 71.43 % ) " "Info: Total cell delay = 0.500 ns ( 71.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns ( 28.57 % ) " "Info: Total interconnect delay = 0.200 ns ( 28.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.700 ns" { keyboard:inst|COUNT:inst|7493:inst1|15 keyboard:inst|COUNT:inst|7493:inst1|15 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.700 ns" { keyboard:inst|COUNT:inst|7493:inst1|15 keyboard:inst|COUNT:inst|7493:inst1|15 } { 0.000ns 0.200ns } { 0.000ns 0.500ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "lie\[0\] destination 7.700 ns + Shortest register " "Info: + Shortest clock path from clock \"lie\[0\]\" to destination register is 7.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns lie\[0\] 1 CLK PIN_67 7 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_67; Fanout = 7; CLK Node = 'lie\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lie[0] } "NODE_NAME" } } { "epasswordlock.bdf" "" { Schematic "D:/altera/ym/text10/epasswordlock/epasswordlock.bdf" { { 80 184 352 96 "lie\[3..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.100 ns) 6.200 ns keyboard:inst\|COUNT:inst\|inst9 2 COMB LC6_E29 1 " "Info: 2: + IC(1.600 ns) + CELL(1.100 ns) = 6.200 ns; Loc. = LC6_E29; Fanout = 1; COMB Node = 'keyboard:inst\|COUNT:inst\|inst9'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.700 ns" { lie[0] keyboard:inst|COUNT:inst|inst9 } "NODE_NAME" } } { "COUNT.bdf" "" { Schematic "D:/altera/ym/text10/epasswordlock/COUNT.bdf" { { 232 96 160 280 "inst9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.400 ns) 6.800 ns keyboard:inst\|COUNT:inst\|7493:inst1\|16 3 REG LC7_E29 7 " "Info: 3: + IC(0.200 ns) + CELL(0.400 ns) = 6.800 ns; Loc. = LC7_E29; Fanout = 7; REG Node = 'keyboard:inst\|COUNT:inst\|7493:inst1\|16'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.600 ns" { keyboard:inst|COUNT:inst|inst9 keyboard:inst|COUNT:inst|7493:inst1|16 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 48 480 544 128 "16" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.000 ns) 7.700 ns keyboard:inst\|COUNT:inst\|7493:inst1\|15 4 REG LC1_E27 6 " "Info: 4: + IC(0.900 ns) + CELL(0.000 ns) = 7.700 ns; Loc. = LC1_E27; Fanout = 6; REG Node = 'keyboard:inst\|COUNT:inst\|7493:inst1\|15'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { keyboard:inst|COUNT:inst|7493:inst1|16 keyboard:inst|COUNT:inst|7493:inst1|15 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 64.94 % ) " "Info: Total cell delay = 5.000 ns ( 64.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 35.06 % ) " "Info: Total interconnect delay = 2.700 ns ( 35.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.700 ns" { lie[0] keyboard:inst|COUNT:inst|inst9 keyboard:inst|COUNT:inst|7493:inst1|16 keyboard:inst|COUNT:inst|7493:inst1|15 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.700 ns" { lie[0] lie[0]~out keyboard:inst|COUNT:inst|inst9 keyboard:inst|COUNT:inst|7493:inst1|16 keyboard:inst|COUNT:inst|7493:inst1|15 } { 0.000ns 0.000ns 1.600ns 0.200ns 0.900ns } { 0.000ns 3.500ns 1.100ns 0.400ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "lie\[0\] source 7.700 ns - Longest register " "Info: - Longest clock path from clock \"lie\[0\]\" to source register is 7.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns lie\[0\] 1 CLK PIN_67 7 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_67; Fanout = 7; CLK Node = 'lie\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lie[0] } "NODE_NAME" } } { "epasswordlock.bdf" "" { Schematic "D:/altera/ym/text10/epasswordlock/epasswordlock.bdf" { { 80 184 352 96 "lie\[3..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.100 ns) 6.200 ns keyboard:inst\|COUNT:inst\|inst9 2 COMB LC6_E29 1 " "Info: 2: + IC(1.600 ns) + CELL(1.100 ns) = 6.200 ns; Loc. = LC6_E29; Fanout = 1; COMB Node = 'keyboard:inst\|COUNT:inst\|inst9'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.700 ns" { lie[0] keyboard:inst|COUNT:inst|inst9 } "NODE_NAME" } } { "COUNT.bdf" "" { Schematic "D:/altera/ym/text10/epasswordlock/COUNT.bdf" { { 232 96 160 280 "inst9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.400 ns) 6.800 ns keyboard:inst\|COUNT:inst\|7493:inst1\|16 3 REG LC7_E29 7 " "Info: 3: + IC(0.200 ns) + CELL(0.400 ns) = 6.800 ns; Loc. = LC7_E29; Fanout = 7; REG Node = 'keyboard:inst\|COUNT:inst\|7493:inst1\|16'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.600 ns" { keyboard:inst|COUNT:inst|inst9 keyboard:inst|COUNT:inst|7493:inst1|16 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 48 480 544 128 "16" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.000 ns) 7.700 ns keyboard:inst\|COUNT:inst\|7493:inst1\|15 4 REG LC1_E27 6 " "Info: 4: + IC(0.900 ns) + CELL(0.000 ns) = 7.700 ns; Loc. = LC1_E27; Fanout = 6; REG Node = 'keyboard:inst\|COUNT:inst\|7493:inst1\|15'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { keyboard:inst|COUNT:inst|7493:inst1|16 keyboard:inst|COUNT:inst|7493:inst1|15 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 64.94 % ) " "Info: Total cell delay = 5.000 ns ( 64.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 35.06 % ) " "Info: Total interconnect delay = 2.700 ns ( 35.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.700 ns" { lie[0] keyboard:inst|COUNT:inst|inst9 keyboard:inst|COUNT:inst|7493:inst1|16 keyboard:inst|COUNT:inst|7493:inst1|15 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.700 ns" { lie[0] lie[0]~out keyboard:inst|COUNT:inst|inst9 keyboard:inst|COUNT:inst|7493:inst1|16 keyboard:inst|COUNT:inst|7493:inst1|15 } { 0.000ns 0.000ns 1.600ns 0.200ns 0.900ns } { 0.000ns 3.500ns 1.100ns 0.400ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.700 ns" { lie[0] keyboard:inst|COUNT:inst|inst9 keyboard:inst|COUNT:inst|7493:inst1|16 keyboard:inst|COUNT:inst|7493:inst1|15 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.700 ns" { lie[0] lie[0]~out keyboard:inst|COUNT:inst|inst9 keyboard:inst|COUNT:inst|7493:inst1|16 keyboard:inst|COUNT:inst|7493:inst1|15 } { 0.000ns 0.000ns 1.600ns 0.200ns 0.900ns } { 0.000ns 3.500ns 1.100ns 0.400ns 0.000ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.700 ns" { lie[0] keyboard:inst|COUNT:inst|inst9 keyboard:inst|COUNT:inst|7493:inst1|16 keyboard:inst|COUNT:inst|7493:inst1|15 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.700 ns" { lie[0] lie[0]~out keyboard:inst|COUNT:inst|inst9 keyboard:inst|COUNT:inst|7493:inst1|16 keyboard:inst|COUNT:inst|7493:inst1|15 } { 0.000ns 0.000ns 1.600ns 0.200ns 0.900ns } { 0.000ns 3.500ns 1.100ns 0.400ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.400 ns + " "Info: + Micro clock to output delay of source is 0.400 ns" {  } { { "7493.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "7493.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.700 ns" { keyboard:inst|COUNT:inst|7493:inst1|15 keyboard:inst|COUNT:inst|7493:inst1|15 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.700 ns" { keyboard:inst|COUNT:inst|7493:inst1|15 keyboard:inst|COUNT:inst|7493:inst1|15 } { 0.000ns 0.200ns } { 0.000ns 0.500ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.700 ns" { lie[0] keyboard:inst|COUNT:inst|inst9 keyboard:inst|COUNT:inst|7493:inst1|16 keyboard:inst|COUNT:inst|7493:inst1|15 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.700 ns" { lie[0] lie[0]~out keyboard:inst|COUNT:inst|inst9 keyboard:inst|COUNT:inst|7493:inst1|16 keyboard:inst|COUNT:inst|7493:inst1|15 } { 0.000ns 0.000ns 1.600ns 0.200ns 0.900ns } { 0.000ns 3.500ns 1.100ns 0.400ns 0.000ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.700 ns" { lie[0] keyboard:inst|COUNT:inst|inst9 keyboard:inst|COUNT:inst|7493:inst1|16 keyboard:inst|COUNT:inst|7493:inst1|15 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.700 ns" { lie[0] lie[0]~out keyboard:inst|COUNT:inst|inst9 keyboard:inst|COUNT:inst|7493:inst1|16 keyboard:inst|COUNT:inst|7493:inst1|15 } { 0.000ns 0.000ns 1.600ns 0.200ns 0.900ns } { 0.000ns 3.500ns 1.100ns 0.400ns 0.000ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { keyboard:inst|COUNT:inst|7493:inst1|15 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { keyboard:inst|COUNT:inst|7493:inst1|15 } {  } {  } } } { "7493.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "lie\[1\] register register keyboard:inst\|COUNT:inst\|7493:inst1\|15 keyboard:inst\|COUNT:inst\|7493:inst1\|15 200.0 MHz Internal " "Info: Clock \"lie\[1\]\" Internal fmax is restricted to 200.0 MHz between source register \"keyboard:inst\|COUNT:inst\|7493:inst1\|15\" and destination register \"keyboard:inst\|COUNT:inst\|7493:inst1\|15\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.700 ns + Longest register register " "Info: + Longest register to register delay is 0.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns keyboard:inst\|COUNT:inst\|7493:inst1\|15 1 REG LC1_E27 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_E27; Fanout = 6; REG Node = 'keyboard:inst\|COUNT:inst\|7493:inst1\|15'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { keyboard:inst|COUNT:inst|7493:inst1|15 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.500 ns) 0.700 ns keyboard:inst\|COUNT:inst\|7493:inst1\|15 2 REG LC1_E27 6 " "Info: 2: + IC(0.200 ns) + CELL(0.500 ns) = 0.700 ns; Loc. = LC1_E27; Fanout = 6; REG Node = 'keyboard:inst\|COUNT:inst\|7493:inst1\|15'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.700 ns" { keyboard:inst|COUNT:inst|7493:inst1|15 keyboard:inst|COUNT:inst|7493:inst1|15 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 71.43 % ) " "Info: Total cell delay = 0.500 ns ( 71.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns ( 28.57 % ) " "Info: Total interconnect delay = 0.200 ns ( 28.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.700 ns" { keyboard:inst|COUNT:inst|7493:inst1|15 keyboard:inst|COUNT:inst|7493:inst1|15 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.700 ns" { keyboard:inst|COUNT:inst|7493:inst1|15 keyboard:inst|COUNT:inst|7493:inst1|15 } { 0.000ns 0.200ns } { 0.000ns 0.500ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "lie\[1\] destination 7.700 ns + Shortest register " "Info: + Shortest clock path from clock \"lie\[1\]\" to destination register is 7.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns lie\[1\] 1 CLK PIN_65 7 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_65; Fanout = 7; CLK Node = 'lie\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lie[1] } "NODE_NAME" } } { "epasswordlock.bdf" "" { Schematic "D:/altera/ym/text10/epasswordlock/epasswordlock.bdf" { { 80 184 352 96 "lie\[3..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.100 ns) 6.200 ns keyboard:inst\|COUNT:inst\|inst9 2 COMB LC6_E29 1 " "Info: 2: + IC(1.600 ns) + CELL(1.100 ns) = 6.200 ns; Loc. = LC6_E29; Fanout = 1; COMB Node = 'keyboard:inst\|COUNT:inst\|inst9'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.700 ns" { lie[1] keyboard:inst|COUNT:inst|inst9 } "NODE_NAME" } } { "COUNT.bdf" "" { Schematic "D:/altera/ym/text10/epasswordlock/COUNT.bdf" { { 232 96 160 280 "inst9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.400 ns) 6.800 ns keyboard:inst\|COUNT:inst\|7493:inst1\|16 3 REG LC7_E29 7 " "Info: 3: + IC(0.200 ns) + CELL(0.400 ns) = 6.800 ns; Loc. = LC7_E29; Fanout = 7; REG Node = 'keyboard:inst\|COUNT:inst\|7493:inst1\|16'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.600 ns" { keyboard:inst|COUNT:inst|inst9 keyboard:inst|COUNT:inst|7493:inst1|16 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 48 480 544 128 "16" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.000 ns) 7.700 ns keyboard:inst\|COUNT:inst\|7493:inst1\|15 4 REG LC1_E27 6 " "Info: 4: + IC(0.900 ns) + CELL(0.000 ns) = 7.700 ns; Loc. = LC1_E27; Fanout = 6; REG Node = 'keyboard:inst\|COUNT:inst\|7493:inst1\|15'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { keyboard:inst|COUNT:inst|7493:inst1|16 keyboard:inst|COUNT:inst|7493:inst1|15 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 64.94 % ) " "Info: Total cell delay = 5.000 ns ( 64.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 35.06 % ) " "Info: Total interconnect delay = 2.700 ns ( 35.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.700 ns" { lie[1] keyboard:inst|COUNT:inst|inst9 keyboard:inst|COUNT:inst|7493:inst1|16 keyboard:inst|COUNT:inst|7493:inst1|15 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.700 ns" { lie[1] lie[1]~out keyboard:inst|COUNT:inst|inst9 keyboard:inst|COUNT:inst|7493:inst1|16 keyboard:inst|COUNT:inst|7493:inst1|15 } { 0.000ns 0.000ns