epasswordlock.tan.qmsg

是一些很好的FPGA设计实例

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk1 " "Info: Assuming node \"clk1\" is an undefined clock" {  } { { "epasswordlock.bdf" "" { Schematic "D:/altera/ym/text10/epasswordlock/epasswordlock.bdf" { { 112 184 352 128 "clk1" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk1" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "epasswordlock.bdf" "" { Schematic "D:/altera/ym/text10/epasswordlock/epasswordlock.bdf" { { 256 128 296 272 "clk" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "lie\[0\] " "Info: Assuming node \"lie\[0\]\" is an undefined clock" {  } { { "epasswordlock.bdf" "" { Schematic "D:/altera/ym/text10/epasswordlock/epasswordlock.bdf" { { 80 184 352 96 "lie\[3..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "lie\[0\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "lie\[1\] " "Info: Assuming node \"lie\[1\]\" is an undefined clock" {  } { { "epasswordlock.bdf" "" { Schematic "D:/altera/ym/text10/epasswordlock/epasswordlock.bdf" { { 80 184 352 96 "lie\[3..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "lie\[1\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "lie\[2\] " "Info: Assuming node \"lie\[2\]\" is an undefined clock" {  } { { "epasswordlock.bdf" "" { Schematic "D:/altera/ym/text10/epasswordlock/epasswordlock.bdf" { { 80 184 352 96 "lie\[3..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "lie\[2\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "lie\[3\] " "Info: Assuming node \"lie\[3\]\" is an undefined clock" {  } { { "epasswordlock.bdf" "" { Schematic "D:/altera/ym/text10/epasswordlock/epasswordlock.bdf" { { 80 184 352 96 "lie\[3..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "lie\[3\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}