epasswordlock.map.qmsg

是一些很好的FPGA设计实例

{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "control.v(35) " "Warning (10273): Verilog HDL warning at control.v(35): extended using \"x\" or \"z\"" {  } { { "control.v" "" { Text "D:/altera/ym/text10/epasswordlock/control.v" 35 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0}
{ "Warning" "WSGN_SEARCH_FILE" "control.v 1 1 " "Warning: Using design file control.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 control " "Info: Found entity 1: control" {  } { { "control.v" "" { Text "D:/altera/ym/text10/epasswordlock/control.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control keyboard:inst\|CONTROL1:inst3\|control:inst " "Info: Elaborating entity \"control\" for hierarchy \"keyboard:inst\|CONTROL1:inst3\|control:inst\"" {  } { { "CONTROL1.bdf" "inst" { Schematic "D:/altera/ym/text10/epasswordlock/CONTROL1.bdf" { { 112 312 464 208 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_GENERIC_WARNING_WITH_LOC" "can't check case statement for completeness because the case expression has too many possible states control.v(26) " "Warning (10005): Verilog HDL or VHDL warning at control.v(26): can't check case statement for completeness because the case expression has too many possible states" {  } { { "control.v" "" { Text "D:/altera/ym/text10/epasswordlock/control.v" 26 0 0 } }  } 0 10005 "Verilog HDL or VHDL warning at %2!s!: %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "KEYVALUE.v(28) " "Warning (10273): Verilog HDL warning at KEYVALUE.v(28): extended using \"x\" or \"z\"" {  } { { "KEYVALUE.v" "" { Text "D:/altera/ym/text10/epasswordlock/KEYVALUE.v" 28 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0}
{ "Warning" "WSGN_SEARCH_FILE" "KEYVALUE.v 1 1 " "Warning: Using design file KEYVALUE.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 KEYVALUE " "Info: Found entity 1: KEYVALUE" {  } { { "KEYVALUE.v" "" { Text "D:/altera/ym/text10/epasswordlock/KEYVALUE.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "KEYVALUE keyboard:inst\|KEYVALUE:inst1 " "Info: Elaborating entity \"KEYVALUE\" for hierarchy \"keyboard:inst\|KEYVALUE:inst1\"" {  } { { "keyboard.bdf" "inst1" { Schematic "D:/altera/ym/text10/epasswordlock/keyboard.bdf" { { 88 312 448 184 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "COUNT.bdf 1 1 " "Warning: Using design file COUNT.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 COUNT " "Info: Found entity 1: COUNT" {  } { { "COUNT.bdf" "" { Schematic "D:/altera/ym/text10/epasswordlock/COUNT.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "COUNT keyboard:inst\|COUNT:inst " "Info: Elaborating entity \"COUNT\" for hierarchy \"keyboard:inst\|COUNT:inst\"" {  } { { "keyboard.bdf" "inst" { Schematic "D:/altera/ym/text10/epasswordlock/keyboard.bdf" { { -8 312 408 88 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "C 74138 inst5 " "Warning: Port \"C\" of type 74138 and instance \"inst5\" is missing source signal" {  } { { "COUNT.bdf" "" { Schematic "D:/altera/ym/text10/epasswordlock/COUNT.bdf" { { 168 376 496 328 "inst5" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../quartus60/libraries/others/maxplus2/74138.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../quartus60/libraries/others/maxplus2/74138.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74138 " "Info: Found entity 1: 74138" {  } { { "74138.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/74138.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74138 keyboard:inst\|COUNT:inst\|74138:inst5 " "Info: Elaborating entity \"74138\" for hierarchy \"keyboard:inst\|COUNT:inst\|74138:inst5\"" {  } { { "COUNT.bdf" "inst5" { Schematic "D:/altera/ym/text10/epasswordlock/COUNT.bdf" { { 168 376 496 328 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "keyboard:inst\|COUNT:inst\|74138:inst5 " "Info: Elaborated megafunction instantiation \"keyboard:inst\|COUNT:inst\|74138:inst5\"" {  } { { "COUNT.bdf" "" { Schematic "D:/altera/ym/text10/epasswordlock/COUNT.bdf" { { 168 376 496 328 "inst5" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "tellpw.v 1 1 " "Warning: Using design file tellpw.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 tellpw " "Info: Found entity 1: tellpw" {  } { { "tellpw.v" "" { Text "D:/altera/ym/text10/epasswordlock/tellpw.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tellpw tellpw:inst19 " "Info: Elaborating entity \"tellpw\" for hierarchy \"tellpw:inst19\"" {  } { { "epasswordlock.bdf" "inst19" { Schematic "D:/altera/ym/text10/epasswordlock/epasswordlock.bdf" { { 216 1064 1232 344 "inst19" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 tellpw.v(19) " "Warning (10230): Verilog HDL assignment warning at tellpw.v(19): truncated value with size 32 to match size of target (2)" {  } { { "tellpw.v" "" { Text "D:/altera/ym/text10/epasswordlock/tellpw.v" 19 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "setpw.v 1 1 " "Warning: Using design file setpw.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 setpw " "Info: Found entity 1: setpw" {  } { { "setpw.v" "" { Text "D:/altera/ym/text10/epasswordlock/setpw.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "setpw setpw:inst4 " "Info: Elaborating entity \"setpw\" for hierarchy \"setpw:inst4\"" {  } { { "epasswordlock.bdf" "inst4" { Schematic "D:/altera/ym/text10/epasswordlock/epasswordlock.bdf" { { 80 1056 1232 208 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "keyboard:inst\|smdisplay:inst4\|74175:inst29\|16 data_in GND " "Warning: Reduced register \"keyboard:inst\|smdisplay:inst4\|74175:inst29\|16\" with stuck data_in port to stuck value GND" {  } { { "74175.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 40 352 416 120 "16" "" } } } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "keyboard:inst\|smdisplay:inst4\|74175:inst29\|15 data_in GND " "Warning: Reduced register \"keyboard:inst\|smdisplay:inst4\|74175:inst29\|15\" with stuck data_in port to stuck value GND" {  } { { "74175.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 184 352 416 264 "15" "" } } } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "keyboard:inst\|smdisplay:inst4\|74175:inst29\|14 data_in GND " "Warning: Reduced register \"keyboard:inst\|smdisplay:inst4\|74175:inst29\|14\" with stuck data_in port to stuck value GND" {  } { { "74175.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 344 352 416 424 "14" "" } } } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "keyboard:inst\|smdisplay:inst4\|74175:inst29\|13 data_in GND " "Warning: Reduced register \"keyboard:inst\|smdisplay:inst4\|74175:inst29\|13\" with stuck data_in port to stuck value GND" {  } { { "74175.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 504 352 416 584 "13" "" } } } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "keyboard:inst\|smdisplay:inst4\|74175:inst28\|16 data_in GND " "Warning: Reduced register \"keyboard:inst\|smdisplay:inst4\|74175:inst28\|16\" with stuck data_in port to stuck value GND" {  } { { "74175.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 40 352 416 120 "16" "" } } } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "keyboard:inst\|smdisplay:inst4\|74175:inst28\|15 data_in GND " "Warning: Reduced register \"keyboard:inst\|smdisplay:inst4\|74175:inst28\|15\" with stuck data_in port to stuck value GND" {  } { { "74175.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 184 352 416 264 "15" "" } } } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "keyboard:inst\|smdisplay:inst4\|74175:inst28\|14 data_in GND " "Warning: Reduced register \"keyboard:inst\|smdisplay:inst4\|74175:inst28\|14\" with stuck data_in port to stuck value GND" {  } { { "74175.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 344 352 416 424 "14" "" } } } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "keyboard:inst\|smdisplay:inst4\|74175:inst28\|13 data_in GND " "Warning: Reduced register \"keyboard:inst\|smdisplay:inst4\|74175:inst28\|13\" with stuck data_in port to stuck value GND" {  } { { "74175.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 504 352 416 584 "13" "" } } } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "keyboard:inst\|CONTROL1:inst3\|control:inst\|i\[0\]~1500 32 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: \"keyboard:inst\|CONTROL1:inst3\|control:inst\|i\[0\]~1500\"" {  } { { "control.v" "i\[0\]~1500" { Text "D:/altera/ym/text10/epasswordlock/control.v" 57 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}