tellpw.v

来自「是一些很好的FPGA设计实例」· Verilog 代码 · 共 33 行

module tellpw(DIN,DATA,cfm,ok,n,lock,mis);
input[23:0] DIN,DATA;
input cfm;
output ok,lock,mis;
output[1:0] n;
reg ok,lock,mis;
reg[1:0] n;
always @(posedge cfm)
 begin
  if(DIN==DATA)
   begin
   n=0;
   lock=0;
   ok=1;
   mis=0;
   end
  else
   begin
   n=n+1;
   ok=0;
   mis=1;
   end
  if(n==3)
   begin
   ok=0;
   lock=1;
   mis=0;
   end
  else
   begin
   end
 end
endmodule