setpw.tan.qmsg

是一些很好的FPGA设计实例

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "cfm " "Info: Assuming node \"cfm\" is an undefined clock" {  } { { "setpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/setpw/setpw.v" 2 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cfm" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "cfm register a\[4\] register DOUT\[6\]~reg0 123.46 MHz 8.1 ns Internal " "Info: Clock \"cfm\" has Internal fmax of 123.46 MHz between source register \"a\[4\]\" and destination register \"DOUT\[6\]~reg0\" (period= 8.1 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.100 ns + Longest register register " "Info: + Longest register to register delay is 7.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns a\[4\] 1 REG LC2_E3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_E3; Fanout = 1; REG Node = 'a\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { a[4] } "NODE_NAME" } } { "setpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/setpw/setpw.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.800 ns) 1.000 ns Equal0~506 2 COMB LC6_E3 1 " "Info: 2: + IC(0.200 ns) + CELL(0.800 ns) = 1.000 ns; Loc. = LC6_E3; Fanout = 1; COMB Node = 'Equal0~506'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.000 ns" { a[4] Equal0~506 } "NODE_NAME" } } { "setpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/setpw/setpw.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 2.200 ns Equal0~486 3 COMB LC7_E3 1 " "Info: 3: + IC(0.000 ns) + CELL(1.200 ns) = 2.200 ns; Loc. = LC7_E3; Fanout = 1; COMB Node = 'Equal0~486'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.200 ns" { Equal0~506 Equal0~486 } "NODE_NAME" } } { "setpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/setpw/setpw.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(1.100 ns) 4.100 ns Equal0~452 4 COMB LC1_E2 2 " "Info: 4: + IC(0.800 ns) + CELL(1.100 ns) = 4.100 ns; Loc. = LC1_E2; Fanout = 2; COMB Node = 'Equal0~452'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { Equal0~486 Equal0~452 } "NODE_NAME" } } { "setpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/setpw/setpw.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.900 ns) 5.200 ns DOUT\[23\]~24 5 COMB LC7_E2 24 " "Info: 5: + IC(0.200 ns) + CELL(0.900 ns) = 5.200 ns; Loc. = LC7_E2; Fanout = 24; COMB Node = 'DOUT\[23\]~24'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.100 ns" { Equal0~452 DOUT[23]~24 } "NODE_NAME" } } { "setpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/setpw/setpw.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(0.800 ns) 7.100 ns DOUT\[6\]~reg0 6 REG LC3_E8 1 " "Info: 6: + IC(1.100 ns) + CELL(0.800 ns) = 7.100 ns; Loc. = LC3_E8; Fanout = 1; REG Node = 'DOUT\[6\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { DOUT[23]~24 DOUT[6]~reg0 } "NODE_NAME" } } { "setpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/setpw/setpw.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.800 ns ( 67.61 % ) " "Info: Total cell delay = 4.800 ns ( 67.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns ( 32.39 % ) " "Info: Total interconnect delay = 2.300 ns ( 32.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.100 ns" { a[4] Equal0~506 Equal0~486 Equal0~452 DOUT[23]~24 DOUT[6]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.100 ns" { a[4] Equal0~506 Equal0~486 Equal0~452 DOUT[23]~24 DOUT[6]~reg0 } { 0.000ns 0.200ns 0.000ns 0.800ns 0.200ns 1.100ns } { 0.000ns 0.800ns 1.200ns 1.100ns 0.900ns 0.800ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cfm destination 1.800 ns + Shortest register " "Info: + Shortest clock path from clock \"cfm\" to destination register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns cfm 1 CLK PIN_79 50 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 50; CLK Node = 'cfm'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cfm } "NODE_NAME" } } { "setpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/setpw/setpw.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.000 ns) 1.800 ns DOUT\[6\]~reg0 2 REG LC3_E8 1 " "Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC3_E8; Fanout = 1; REG Node = 'DOUT\[6\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { cfm DOUT[6]~reg0 } "NODE_NAME" } } { "setpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/setpw/setpw.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 83.33 % ) " "Info: Total cell delay = 1.500 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.300 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { cfm DOUT[6]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { cfm cfm~out DOUT[6]~reg0 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cfm source 1.800 ns - Longest register " "Info: - Longest clock path from clock \"cfm\" to source register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns cfm 1 CLK PIN_79 50 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 50; CLK Node = 'cfm'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cfm } "NODE_NAME" } } { "setpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/setpw/setpw.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.000 ns) 1.800 ns a\[4\] 2 REG LC2_E3 1 " "Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC2_E3; Fanout = 1; REG Node = 'a\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { cfm a[4] } "NODE_NAME" } } { "setpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/setpw/setpw.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 83.33 % ) " "Info: Total cell delay = 1.500 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.300 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { cfm a[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { cfm cfm~out a[4] } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { cfm DOUT[6]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { cfm cfm~out DOUT[6]~reg0 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { cfm a[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { cfm cfm~out a[4] } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.400 ns + " "Info: + Micro clock to output delay of source is 0.400 ns" {  } { { "setpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/setpw/setpw.v" 33 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "setpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/setpw/setpw.v" 33 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.100 ns" { a[4] Equal0~506 Equal0~486 Equal0~452 DOUT[23]~24 DOUT[6]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.100 ns" { a[4] Equal0~506 Equal0~486 Equal0~452 DOUT[23]~24 DOUT[6]~reg0 } { 0.000ns 0.200ns 0.000ns 0.800ns 0.200ns 1.100ns } { 0.000ns 0.800ns 1.200ns 1.100ns 0.900ns 0.800ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { cfm DOUT[6]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { cfm cfm~out DOUT[6]~reg0 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { cfm a[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { cfm cfm~out a[4] } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "DOUT\[6\]~reg0 DATA\[18\] cfm 11.400 ns register " "Info: tsu for register \"DOUT\[6\]~reg0\" (data pin = \"DATA\[18\]\", clock pin = \"cfm\") is 11.400 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.600 ns + Longest pin register " "Info: + Longest pin to register delay is 12.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns DATA\[18\] 1 PIN PIN_38 3 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_38; Fanout = 3; PIN Node = 'DATA\[18\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA[18] } "NODE_NAME" } } { "setpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/setpw/setpw.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(0.700 ns) 6.500 ns Equal0~509 2 COMB LC1_E5 1 " "Info: 2: + IC(2.300 ns) + CELL(0.700 ns) = 6.500 ns; Loc. = LC1_E5; Fanout = 1; COMB Node = 'Equal0~509'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.000 ns" { DATA[18] Equal0~509 } "NODE_NAME" } } { "setpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/setpw/setpw.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 7.700 ns Equal0~487 3 COMB LC2_E5 1 " "Info: 3: + IC(0.000 ns) + CELL(1.200 ns) = 7.700 ns; Loc. = LC2_E5; Fanout = 1; COMB Node = 'Equal0~487'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.200 ns" { Equal0~509 Equal0~487 } "NODE_NAME" } } { "setpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/setpw/setpw.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(1.100 ns) 9.600 ns Equal0~452 4 COMB LC1_E2 2 " "Info: 4: + IC(0.800 ns) + CELL(1.100 ns) = 9.600 ns; Loc. = LC1_E2; Fanout = 2; COMB Node = 'Equal0~452'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { Equal0~487 Equal0~452 } "NODE_NAME" } } { "setpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/setpw/setpw.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.900 ns) 10.700 ns DOUT\[23\]~24 5 COMB LC7_E2 24 " "Info: 5: + IC(0.200 ns) + CELL(0.900 ns) = 10.700 ns; Loc. = LC7_E2; Fanout = 24; COMB Node = 'DOUT\[23\]~24'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.100 ns" { Equal0~452 DOUT[23]~24 } "NODE_NAME" } } { "setpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/setpw/setpw.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(0.800 ns) 12.600 ns DOUT\[6\]~reg0 6 REG LC3_E8 1 " "Info: 6: + IC(1.100 ns) + CELL(0.800 ns) = 12.600 ns; Loc. = LC3_E8; Fanout = 1; REG Node = 'DOUT\[6\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { DOUT[23]~24 DOUT[6]~reg0 } "NODE_NAME" } } { "setpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/setpw/setpw.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.200 ns ( 65.08 % ) " "Info: Total cell delay = 8.200 ns ( 65.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.400 ns ( 34.92 % ) " "Info: Total interconnect delay = 4.400 ns ( 34.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.600 ns" { DATA[18] Equal0~509 Equal0~487 Equal0~452 DOUT[23]~24 DOUT[6]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.600 ns" { DATA[18] DATA[18]~out Equal0~509 Equal0~487 Equal0~452 DOUT[23]~24 DOUT[6]~reg0 } { 0.000ns 0.000ns 2.300ns 0.000ns 0.800ns 0.200ns 1.100ns } { 0.000ns 3.500ns 0.700ns 1.200ns 1.100ns 0.900ns 0.800ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "setpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/setpw/setpw.v" 33 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cfm destination 1.800 ns - Shortest register " "Info: - Shortest clock path from clock \"cfm\" to destination register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns cfm 1 CLK PIN_79 50 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 50; CLK Node = 'cfm'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cfm } "NODE_NAME" } } { "setpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/setpw/setpw.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.000 ns) 1.800 ns DOUT\[6\]~reg0 2 REG LC3_E8 1 " "Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC3_E8; Fanout = 1; REG Node = 'DOUT\[6\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { cfm DOUT[6]~reg0 } "NODE_NAME" } } { "setpw.v" "" { Text "C:/altera/ym/text10/epasswordlock/setpw/setpw.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 83.33 % ) " "Info: Total cell delay = 1.500 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.300 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { cfm DOUT[6]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { cfm cfm~out DOUT[6]~reg0 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.600 ns" { DATA[18] Equal0~509 Equal0~487 Equal0~452 DOUT[23]~24 DOUT[6]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.600 ns" { DATA[18] DATA[18]~out Equal0~509 Equal0~487 Equal0~452 DOUT[23]~24 DOUT[6]~reg0 } { 0.000ns 0.000ns 2.300ns 0.000ns 0.800ns 0.200ns 1.100ns } { 0.000ns 3.500ns 0.700ns 1.200ns 1.100ns 0.900ns 0.800ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { cfm DOUT[6]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { cfm cfm~out DOUT[6]~reg0 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}