📄 led_display.tan.rpt
字号:
; N/A ; None ; 18.500 ns ; 7493:inst1|16 ; q[13] ; CLK ;
; N/A ; None ; 18.500 ns ; 7493:inst1|16 ; q[15] ; CLK ;
; N/A ; None ; 18.300 ns ; 7493:inst1|16 ; q[0] ; CLK ;
; N/A ; None ; 18.200 ns ; 7493:inst1|16 ; q[1] ; CLK ;
; N/A ; None ; 18.200 ns ; 7493:inst1|16 ; q[2] ; CLK ;
; N/A ; None ; 18.200 ns ; 7493:inst1|16 ; q[3] ; CLK ;
; N/A ; None ; 18.200 ns ; 7493:inst1|16 ; q[4] ; CLK ;
; N/A ; None ; 18.200 ns ; 7493:inst1|16 ; q[6] ; CLK ;
; N/A ; None ; 18.200 ns ; 7493:inst1|16 ; q[8] ; CLK ;
; N/A ; None ; 18.100 ns ; 7493:inst1|16 ; q[7] ; CLK ;
; N/A ; None ; 18.100 ns ; 7493:inst1|16 ; q[9] ; CLK ;
; N/A ; None ; 11.000 ns ; 7493:inst1|13 ; L4 ; CLK ;
; N/A ; None ; 11.000 ns ; 7493:inst1|14 ; L3 ; CLK ;
; N/A ; None ; 11.000 ns ; 7493:inst1|15 ; L2 ; CLK ;
; N/A ; None ; 10.000 ns ; 7493:inst1|16 ; L1 ; CLK ;
+-------+--------------+------------+---------------+-------+------------+
+---------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+---------+-------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+---------+-------+
; N/A ; None ; 21.900 ns ; addr[4] ; q[11] ;
; N/A ; None ; 21.400 ns ; addr[5] ; q[11] ;
; N/A ; None ; 21.400 ns ; addr[6] ; q[11] ;
; N/A ; None ; 21.400 ns ; addr[7] ; q[11] ;
; N/A ; None ; 20.700 ns ; addr[4] ; q[5] ;
; N/A ; None ; 20.500 ns ; addr[4] ; q[13] ;
; N/A ; None ; 20.500 ns ; addr[4] ; q[15] ;
; N/A ; None ; 20.400 ns ; addr[4] ; q[12] ;
; N/A ; None ; 20.400 ns ; addr[4] ; q[14] ;
; N/A ; None ; 20.300 ns ; addr[4] ; q[10] ;
; N/A ; None ; 20.200 ns ; addr[4] ; q[1] ;
; N/A ; None ; 20.200 ns ; addr[4] ; q[3] ;
; N/A ; None ; 20.200 ns ; addr[5] ; q[5] ;
; N/A ; None ; 20.200 ns ; addr[6] ; q[5] ;
; N/A ; None ; 20.200 ns ; addr[7] ; q[5] ;
; N/A ; None ; 20.100 ns ; addr[4] ; q[0] ;
; N/A ; None ; 20.100 ns ; addr[4] ; q[7] ;
; N/A ; None ; 20.100 ns ; addr[4] ; q[9] ;
; N/A ; None ; 20.000 ns ; addr[4] ; q[2] ;
; N/A ; None ; 20.000 ns ; addr[4] ; q[4] ;
; N/A ; None ; 20.000 ns ; addr[4] ; q[6] ;
; N/A ; None ; 20.000 ns ; addr[4] ; q[8] ;
; N/A ; None ; 20.000 ns ; addr[5] ; q[13] ;
; N/A ; None ; 20.000 ns ; addr[6] ; q[13] ;
; N/A ; None ; 20.000 ns ; addr[7] ; q[13] ;
; N/A ; None ; 20.000 ns ; addr[5] ; q[15] ;
; N/A ; None ; 20.000 ns ; addr[6] ; q[15] ;
; N/A ; None ; 20.000 ns ; addr[7] ; q[15] ;
; N/A ; None ; 19.900 ns ; addr[5] ; q[12] ;
; N/A ; None ; 19.900 ns ; addr[6] ; q[12] ;
; N/A ; None ; 19.900 ns ; addr[7] ; q[12] ;
; N/A ; None ; 19.900 ns ; addr[5] ; q[14] ;
; N/A ; None ; 19.900 ns ; addr[6] ; q[14] ;
; N/A ; None ; 19.900 ns ; addr[7] ; q[14] ;
; N/A ; None ; 19.800 ns ; addr[5] ; q[10] ;
; N/A ; None ; 19.800 ns ; addr[6] ; q[10] ;
; N/A ; None ; 19.800 ns ; addr[7] ; q[10] ;
; N/A ; None ; 19.700 ns ; addr[5] ; q[1] ;
; N/A ; None ; 19.700 ns ; addr[6] ; q[1] ;
; N/A ; None ; 19.700 ns ; addr[7] ; q[1] ;
; N/A ; None ; 19.700 ns ; addr[5] ; q[3] ;
; N/A ; None ; 19.700 ns ; addr[6] ; q[3] ;
; N/A ; None ; 19.700 ns ; addr[7] ; q[3] ;
; N/A ; None ; 19.600 ns ; addr[5] ; q[0] ;
; N/A ; None ; 19.600 ns ; addr[6] ; q[0] ;
; N/A ; None ; 19.600 ns ; addr[7] ; q[0] ;
; N/A ; None ; 19.600 ns ; addr[5] ; q[7] ;
; N/A ; None ; 19.600 ns ; addr[6] ; q[7] ;
; N/A ; None ; 19.600 ns ; addr[7] ; q[7] ;
; N/A ; None ; 19.600 ns ; addr[5] ; q[9] ;
; N/A ; None ; 19.600 ns ; addr[6] ; q[9] ;
; N/A ; None ; 19.600 ns ; addr[7] ; q[9] ;
; N/A ; None ; 19.500 ns ; addr[5] ; q[2] ;
; N/A ; None ; 19.500 ns ; addr[6] ; q[2] ;
; N/A ; None ; 19.500 ns ; addr[7] ; q[2] ;
; N/A ; None ; 19.500 ns ; addr[5] ; q[4] ;
; N/A ; None ; 19.500 ns ; addr[6] ; q[4] ;
; N/A ; None ; 19.500 ns ; addr[7] ; q[4] ;
; N/A ; None ; 19.500 ns ; addr[5] ; q[6] ;
; N/A ; None ; 19.500 ns ; addr[6] ; q[6] ;
; N/A ; None ; 19.500 ns ; addr[7] ; q[6] ;
; N/A ; None ; 19.500 ns ; addr[5] ; q[8] ;
; N/A ; None ; 19.500 ns ; addr[6] ; q[8] ;
; N/A ; None ; 19.500 ns ; addr[7] ; q[8] ;
+-------+-------------------+-----------------+---------+-------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Fri Mar 02 03:07:31 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off LED_DISPLAY -c LED_DISPLAY
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "CLK" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected ripple clock "7493:inst1|16" as buffer
Info: Clock "CLK" Internal fmax is restricted to 200.0 MHz between source register "7493:inst1|14" and destination register "7493:inst1|13"
Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 2.900 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_C7; Fanout = 19; REG Node = '7493:inst1|14'
Info: 2: + IC(0.200 ns) + CELL(1.100 ns) = 1.300 ns; Loc. = LC1_C7; Fanout = 1; COMB Node = '7493:inst1|39'
Info: 3: + IC(0.800 ns) + CELL(0.800 ns) = 2.900 ns; Loc. = LC1_C6; Fanout = 18; REG Node = '7493:inst1|13'
Info: Total cell delay = 1.900 ns ( 65.52 % )
Info: Total interconnect delay = 1.000 ns ( 34.48 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "CLK" to destination register is 5.400 ns
Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 1; CLK Node = 'CLK'
Info: 2: + IC(0.300 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC1_C8; Fanout = 21; REG Node = '7493:inst1|16'
Info: 3: + IC(3.200 ns) + CELL(0.000 ns) = 5.400 ns; Loc. = LC1_C6; Fanout = 18; REG Node = '7493:inst1|13'
Info: Total cell delay = 1.900 ns ( 35.19 % )
Info: Total interconnect delay = 3.500 ns ( 64.81 % )
Info: - Longest clock path from clock "CLK" to source register is 5.400 ns
Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 1; CLK Node = 'CLK'
Info: 2: + IC(0.300 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC1_C8; Fanout = 21; REG Node = '7493:inst1|16'
Info: 3: + IC(3.200 ns) + CELL(0.000 ns) = 5.400 ns; Loc. = LC2_C7; Fanout = 19; REG Node = '7493:inst1|14'
Info: Total cell delay = 1.900 ns ( 35.19 % )
Info: Total interconnect delay = 3.500 ns ( 64.81 % )
Info: + Micro clock to output delay of source is 0.400 ns
Info: + Micro setup delay of destination is 0.600 ns
Info: tco from clock "CLK" to destination pin "q[11]" through register "7493:inst1|15" is 23.600 ns
Info: + Longest clock path from clock "CLK" to source register is 5.400 ns
Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 1; CLK Node = 'CLK'
Info: 2: + IC(0.300 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC1_C8; Fanout = 21; REG Node = '7493:inst1|16'
Info: 3: + IC(3.200 ns) + CELL(0.000 ns) = 5.400 ns; Loc. = LC5_C7; Fanout = 20; REG Node = '7493:inst1|15'
Info: Total cell delay = 1.900 ns ( 35.19 % )
Info: Total interconnect delay = 3.500 ns ( 64.81 % )
Info: + Micro clock to output delay of source is 0.400 ns
Info: + Longest register to pin delay is 17.800 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_C7; Fanout = 20; REG Node = '7493:inst1|15'
Info: 2: + IC(2.100 ns) + CELL(5.600 ns) = 7.700 ns; Loc. = EC7_F; Fanout = 1; MEM Node = 'lpm_rom:inst|altrom:srom|q[11]~mem_cell_ra0'
Info: 3: + IC(0.000 ns) + CELL(1.200 ns) = 8.900 ns; Loc. = EC7_F; Fanout = 1; MEM Node = 'lpm_rom:inst|altrom:srom|q[11]'
Info: 4: + IC(2.700 ns) + CELL(0.900 ns) = 12.500 ns; Loc. = LC1_B20; Fanout = 1; COMB Node = 'q[11]~4'
Info: 5: + IC(0.700 ns) + CELL(4.600 ns) = 17.800 ns; Loc. = PIN_74; Fanout = 0; PIN Node = 'q[11]'
Info: Total cell delay = 12.300 ns ( 69.10 % )
Info: Total interconnect delay = 5.500 ns ( 30.90 % )
Info: Longest tpd from source pin "addr[4]" to destination pin "q[11]" is 21.900 ns
Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_53; Fanout = 16; PIN Node = 'addr[4]'
Info: 2: + IC(2.700 ns) + CELL(5.600 ns) = 11.800 ns; Loc. = EC7_F; Fanout = 1; MEM Node = 'lpm_rom:inst|altrom:srom|q[11]~mem_cell_ra0'
Info: 3: + IC(0.000 ns) + CELL(1.200 ns) = 13.000 ns; Loc. = EC7_F; Fanout = 1; MEM Node = 'lpm_rom:inst|altrom:srom|q[11]'
Info: 4: + IC(2.700 ns) + CELL(0.900 ns) = 16.600 ns; Loc. = LC1_B20; Fanout = 1; COMB Node = 'q[11]~4'
Info: 5: + IC(0.700 ns) + CELL(4.600 ns) = 21.900 ns; Loc. = PIN_74; Fanout = 0; PIN Node = 'q[11]'
Info: Total cell delay = 15.800 ns ( 72.15 % )
Info: Total interconnect delay = 6.100 ns ( 27.85 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
Info: Processing ended: Fri Mar 02 03:07:32 2007
Info: Elapsed time: 00:00:01
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