adder_1.hif

是一些很好的FPGA设计实例

Version 6.0 Build 178 04/27/2006 SJ Full Version
18
887
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
adder_1
# storage
db|adder_1.(0).cnf
db|adder_1.(0).cnf
# case_insensitive
# source_file
adder_1.bdf
9291ed95699eb611c238ad7c56359c5
24
# hierarchies {
|
}
# end
# complete