odd_fren.map.qmsg

是一些很好的FPGA设计实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 01 09:38:48 2008 " "Info: Processing started: Wed Oct 01 09:38:48 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Odd_Fren -c Odd_Fren " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Odd_Fren -c Odd_Fren" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Odd_Fren.vhd 4 2 " "Info: Found 4 design units, including 2 entities, in source file Odd_Fren.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Odd_Fren-bev " "Info: Found design unit 1: Odd_Fren-bev" {  } { { "Odd_Fren.vhd" "" { Text "C:/desk/f_div 3/Odd_Fren.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 tst_Odd_Fren-test " "Info: Found design unit 2: tst_Odd_Fren-test" {  } { { "Odd_Fren.vhd" "" { Text "C:/desk/f_div 3/Odd_Fren.vhd" 61 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 Odd_Fren " "Info: Found entity 1: Odd_Fren" {  } { { "Odd_Fren.vhd" "" { Text "C:/desk/f_div 3/Odd_Fren.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 tst_Odd_Fren " "Info: Found entity 2: tst_Odd_Fren" {  } { { "Odd_Fren.vhd" "" { Text "C:/desk/f_div 3/Odd_Fren.vhd" 59 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Odd_Fren " "Info: Elaborating entity \"Odd_Fren\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "O_t O~reg0 " "Info: Duplicate register \"O_t\" merged to single register \"O~reg0\", power-up level changed" {  } { { "Odd_Fren.vhd" "" { Text "C:/desk/f_div 3/Odd_Fren.vhd" 13 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "O_r\[1\] O_ro " "Info: Duplicate register \"O_r\[1\]\" merged to single register \"O_ro\"" {  } { { "Odd_Fren.vhd" "" { Text "C:/desk/f_div 3/Odd_Fren.vhd" 17 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "Clk " "Info: Promoted clock signal driven by pin \"Clk\" to global clock signal" {  } {  } 0 0 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0}  } {  } 0 0 "Promoted pin-driven signal(s) to global signal" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "10 " "Info: Implemented 10 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_MCELLS" "6 " "Info: Implemented 6 macrocells" {  } {  } 0 0 "Implemented %1!d! macrocells" 0 0} { "Info" "ISCL_SCL_TM_SEXPS" "2 " "Info: Implemented 2 shareable expanders" {  } {  } 0 0 "Implemented %1!d! shareable expanders" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 01 09:38:49 2008 " "Info: Processing ended: Wed Oct 01 09:38:49 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}