clkdiv.tan.qmsg

是一些很好的FPGA设计实例

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "clkdiv.vhd" "" { Text "C:/desk/f/clkdiv.vhd" 8 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lpm_counter:count_rtl_0\|dffs\[0\] register lpm_counter:count_rtl_0\|dffs\[0\] 100.0 MHz 10.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 100.0 MHz between source register \"lpm_counter:count_rtl_0\|dffs\[0\]\" and destination register \"lpm_counter:count_rtl_0\|dffs\[0\]\" (period= 10.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Longest register register " "Info: + Longest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:count_rtl_0\|dffs\[0\] 1 REG LC1 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 7; REG Node = 'lpm_counter:count_rtl_0\|dffs\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_counter:count_rtl_0|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.000 ns) 6.000 ns lpm_counter:count_rtl_0\|dffs\[0\] 2 REG LC1 7 " "Info: 2: + IC(0.000 ns) + CELL(6.000 ns) = 6.000 ns; Loc. = LC1; Fanout = 7; REG Node = 'lpm_counter:count_rtl_0\|dffs\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.000 ns" { lpm_counter:count_rtl_0|dffs[0] lpm_counter:count_rtl_0|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns ( 100.00 % ) " "Info: Total cell delay = 6.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.000 ns" { lpm_counter:count_rtl_0|dffs[0] lpm_counter:count_rtl_0|dffs[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.000 ns" { lpm_counter:count_rtl_0|dffs[0] lpm_counter:count_rtl_0|dffs[0] } { 0.000ns 0.000ns } { 0.000ns 6.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.500 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_83 6 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clkdiv.vhd" "" { Text "C:/desk/f/clkdiv.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns lpm_counter:count_rtl_0\|dffs\[0\] 2 REG LC1 7 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC1; Fanout = 7; REG Node = 'lpm_counter:count_rtl_0\|dffs\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.000 ns" { clk lpm_counter:count_rtl_0|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { clk lpm_counter:count_rtl_0|dffs[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { clk clk~out lpm_counter:count_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.500 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_83 6 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clkdiv.vhd" "" { Text "C:/desk/f/clkdiv.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns lpm_counter:count_rtl_0\|dffs\[0\] 2 REG LC1 7 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC1; Fanout = 7; REG Node = 'lpm_counter:count_rtl_0\|dffs\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.000 ns" { clk lpm_counter:count_rtl_0|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { clk lpm_counter:count_rtl_0|dffs[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { clk clk~out lpm_counter:count_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { clk lpm_counter:count_rtl_0|dffs[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { clk clk~out lpm_counter:count_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { clk lpm_counter:count_rtl_0|dffs[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { clk clk~out lpm_counter:count_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.000 ns" { lpm_counter:count_rtl_0|dffs[0] lpm_counter:count_rtl_0|dffs[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.000 ns" { lpm_counter:count_rtl_0|dffs[0] lpm_counter:count_rtl_0|dffs[0] } { 0.000ns 0.000ns } { 0.000ns 6.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { clk lpm_counter:count_rtl_0|dffs[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { clk clk~out lpm_counter:count_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { clk lpm_counter:count_rtl_0|dffs[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { clk clk~out lpm_counter:count_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk clk_div16 lpm_counter:count_rtl_0\|dffs\[5\] 5.000 ns register " "Info: tco from clock \"clk\" to destination pin \"clk_div16\" through register \"lpm_counter:count_rtl_0\|dffs\[5\]\" is 5.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.500 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_83 6 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clkdiv.vhd" "" { Text "C:/desk/f/clkdiv.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns lpm_counter:count_rtl_0\|dffs\[5\] 2 REG LC4 2 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC4; Fanout = 2; REG Node = 'lpm_counter:count_rtl_0\|dffs\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.000 ns" { clk lpm_counter:count_rtl_0|dffs[5] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { clk lpm_counter:count_rtl_0|dffs[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { clk clk~out lpm_counter:count_rtl_0|dffs[5] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.500 ns + Longest register pin " "Info: + Longest register to pin delay is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:count_rtl_0\|dffs\[5\] 1 REG LC4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4; Fanout = 2; REG Node = 'lpm_counter:count_rtl_0\|dffs\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_counter:count_rtl_0|dffs[5] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk_div16 2 PIN PIN_18 0 " "Info: 2: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_18; Fanout = 0; PIN Node = 'clk_div16'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { lpm_counter:count_rtl_0|dffs[5] clk_div16 } "NODE_NAME" } } { "clkdiv.vhd" "" { Text "C:/desk/f/clkdiv.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { lpm_counter:count_rtl_0|dffs[5] clk_div16 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { lpm_counter:count_rtl_0|dffs[5] clk_div16 } { 0.000ns 0.000ns } { 0.000ns 1.500ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { clk lpm_counter:count_rtl_0|dffs[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { clk clk~out lpm_counter:count_rtl_0|dffs[5] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { lpm_counter:count_rtl_0|dffs[5] clk_div16 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { lpm_counter:count_rtl_0|dffs[5] clk_div16 } { 0.000ns 0.000ns } { 0.000ns 1.500ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 30 15:22:37 2008 " "Info: Processing ended: Tue Sep 30 15:22:37 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}