trafficlight.tan.qmsg

是一些很好的FPGA设计实例

{ "Info" "ITDB_TH_RESULT" "counter55:inst2\|CData0\[0\] Reset CLK 3.781 ns register " "Info: th for register \"counter55:inst2\|CData0\[0\]\" (data pin = \"Reset\", clock pin = \"CLK\") is 3.781 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 9.200 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 9.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK 1 CLK PIN_10 33 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 33; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "trafficlight.bdf" "" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/trafficlight.bdf" { { 776 240 408 792 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.430 ns) + CELL(0.720 ns) 2.280 ns fdiv1khz:inst12\|clk_out 2 REG LC_X8_Y6_N6 34 " "Info: 2: + IC(0.430 ns) + CELL(0.720 ns) = 2.280 ns; Loc. = LC_X8_Y6_N6; Fanout = 34; REG Node = 'fdiv1khz:inst12\|clk_out'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.150 ns" { CLK fdiv1khz:inst12|clk_out } "NODE_NAME" } } { "fdiv1khz.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/fdiv1khz.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.656 ns) + CELL(0.720 ns) 5.656 ns fdiv1hz:inst11\|clk_out 3 REG LC_X11_Y6_N6 14 " "Info: 3: + IC(2.656 ns) + CELL(0.720 ns) = 5.656 ns; Loc. = LC_X11_Y6_N6; Fanout = 14; REG Node = 'fdiv1hz:inst11\|clk_out'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.376 ns" { fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out } "NODE_NAME" } } { "fdiv1hz.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/fdiv1hz.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.997 ns) + CELL(0.547 ns) 9.200 ns counter55:inst2\|CData0\[0\] 4 REG LC_X22_Y11_N3 7 " "Info: 4: + IC(2.997 ns) + CELL(0.547 ns) = 9.200 ns; Loc. = LC_X22_Y11_N3; Fanout = 7; REG Node = 'counter55:inst2\|CData0\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.544 ns" { fdiv1hz:inst11|clk_out counter55:inst2|CData0[0] } "NODE_NAME" } } { "counter55.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter55.v" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.117 ns ( 33.88 % ) " "Info: Total cell delay = 3.117 ns ( 33.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.083 ns ( 66.12 % ) " "Info: Total interconnect delay = 6.083 ns ( 66.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.200 ns" { CLK fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter55:inst2|CData0[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.200 ns" { CLK CLK~out0 fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter55:inst2|CData0[0] } { 0.000ns 0.000ns 0.430ns 2.656ns 2.997ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" {  } { { "counter55.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter55.v" 53 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.431 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.431 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns Reset 1 PIN PIN_79 16 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_79; Fanout = 16; PIN Node = 'Reset'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Reset } "NODE_NAME" } } { "trafficlight.bdf" "" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/trafficlight.bdf" { { 728 240 408 744 "Reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.928 ns) + CELL(0.368 ns) 5.431 ns counter55:inst2\|CData0\[0\] 2 REG LC_X22_Y11_N3 7 " "Info: 2: + IC(3.928 ns) + CELL(0.368 ns) = 5.431 ns; Loc. = LC_X22_Y11_N3; Fanout = 7; REG Node = 'counter55:inst2\|CData0\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.296 ns" { Reset counter55:inst2|CData0[0] } "NODE_NAME" } } { "counter55.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter55.v" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.503 ns ( 27.67 % ) " "Info: Total cell delay = 1.503 ns ( 27.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.928 ns ( 72.33 % ) " "Info: Total interconnect delay = 3.928 ns ( 72.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.431 ns" { Reset counter55:inst2|CData0[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.431 ns" { Reset Reset~out0 counter55:inst2|CData0[0] } { 0.000ns 0.000ns 3.928ns } { 0.000ns 1.135ns 0.368ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.200 ns" { CLK fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter55:inst2|CData0[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.200 ns" { CLK CLK~out0 fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter55:inst2|CData0[0] } { 0.000ns 0.000ns 0.430ns 2.656ns 2.997ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.547ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.431 ns" { Reset counter55:inst2|CData0[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.431 ns" { Reset Reset~out0 counter55:inst2|CData0[0] } { 0.000ns 0.000ns 3.928ns } { 0.000ns 1.135ns 0.368ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu May 22 20:57:55 2008 " "Info: Processing ended: Thu May 22 20:57:55 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}