trafficlight.tan.qmsg

是一些很好的FPGA设计实例

{ "Info" "ITDB_TSU_RESULT" "counter55:inst2\|CData0\[3\] Reset CLK -2.809 ns register " "Info: tsu for register \"counter55:inst2\|CData0\[3\]\" (data pin = \"Reset\", clock pin = \"CLK\") is -2.809 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.362 ns + Longest pin register " "Info: + Longest pin to register delay is 6.362 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns Reset 1 PIN PIN_79 16 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_79; Fanout = 16; PIN Node = 'Reset'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Reset } "NODE_NAME" } } { "trafficlight.bdf" "" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/trafficlight.bdf" { { 728 240 408 744 "Reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.960 ns) + CELL(0.454 ns) 5.549 ns counter55:inst2\|CData0~262 2 COMB LC_X21_Y11_N7 3 " "Info: 2: + IC(3.960 ns) + CELL(0.454 ns) = 5.549 ns; Loc. = LC_X21_Y11_N7; Fanout = 3; COMB Node = 'counter55:inst2\|CData0~262'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.414 ns" { Reset counter55:inst2|CData0~262 } "NODE_NAME" } } { "counter55.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter55.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.575 ns) + CELL(0.238 ns) 6.362 ns counter55:inst2\|CData0\[3\] 3 REG LC_X22_Y11_N2 7 " "Info: 3: + IC(0.575 ns) + CELL(0.238 ns) = 6.362 ns; Loc. = LC_X22_Y11_N2; Fanout = 7; REG Node = 'counter55:inst2\|CData0\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.813 ns" { counter55:inst2|CData0~262 counter55:inst2|CData0[3] } "NODE_NAME" } } { "counter55.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter55.v" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.827 ns ( 28.72 % ) " "Info: Total cell delay = 1.827 ns ( 28.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.535 ns ( 71.28 % ) " "Info: Total interconnect delay = 4.535 ns ( 71.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.362 ns" { Reset counter55:inst2|CData0~262 counter55:inst2|CData0[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.362 ns" { Reset Reset~out0 counter55:inst2|CData0~262 counter55:inst2|CData0[3] } { 0.000ns 0.000ns 3.960ns 0.575ns } { 0.000ns 1.135ns 0.454ns 0.238ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "counter55.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter55.v" 53 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 9.200 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 9.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK 1 CLK PIN_10 33 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 33; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "trafficlight.bdf" "" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/trafficlight.bdf" { { 776 240 408 792 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.430 ns) + CELL(0.720 ns) 2.280 ns fdiv1khz:inst12\|clk_out 2 REG LC_X8_Y6_N6 34 " "Info: 2: + IC(0.430 ns) + CELL(0.720 ns) = 2.280 ns; Loc. = LC_X8_Y6_N6; Fanout = 34; REG Node = 'fdiv1khz:inst12\|clk_out'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.150 ns" { CLK fdiv1khz:inst12|clk_out } "NODE_NAME" } } { "fdiv1khz.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/fdiv1khz.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.656 ns) + CELL(0.720 ns) 5.656 ns fdiv1hz:inst11\|clk_out 3 REG LC_X11_Y6_N6 14 " "Info: 3: + IC(2.656 ns) + CELL(0.720 ns) = 5.656 ns; Loc. = LC_X11_Y6_N6; Fanout = 14; REG Node = 'fdiv1hz:inst11\|clk_out'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.376 ns" { fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out } "NODE_NAME" } } { "fdiv1hz.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/fdiv1hz.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.997 ns) + CELL(0.547 ns) 9.200 ns counter55:inst2\|CData0\[3\] 4 REG LC_X22_Y11_N2 7 " "Info: 4: + IC(2.997 ns) + CELL(0.547 ns) = 9.200 ns; Loc. = LC_X22_Y11_N2; Fanout = 7; REG Node = 'counter55:inst2\|CData0\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.544 ns" { fdiv1hz:inst11|clk_out counter55:inst2|CData0[3] } "NODE_NAME" } } { "counter55.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter55.v" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.117 ns ( 33.88 % ) " "Info: Total cell delay = 3.117 ns ( 33.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.083 ns ( 66.12 % ) " "Info: Total interconnect delay = 6.083 ns ( 66.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.200 ns" { CLK fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter55:inst2|CData0[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.200 ns" { CLK CLK~out0 fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter55:inst2|CData0[3] } { 0.000ns 0.000ns 0.430ns 2.656ns 2.997ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.362 ns" { Reset counter55:inst2|CData0~262 counter55:inst2|CData0[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.362 ns" { Reset Reset~out0 counter55:inst2|CData0~262 counter55:inst2|CData0[3] } { 0.000ns 0.000ns 3.960ns 0.575ns } { 0.000ns 1.135ns 0.454ns 0.238ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.200 ns" { CLK fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter55:inst2|CData0[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.200 ns" { CLK CLK~out0 fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter55:inst2|CData0[3] } { 0.000ns 0.000ns 0.430ns 2.656ns 2.997ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.547ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK SEG_Data\[2\] scan:inst\|sdata\[0\] 23.986 ns register " "Info: tco from clock \"CLK\" to destination pin \"SEG_Data\[2\]\" through register \"scan:inst\|sdata\[0\]\" is 23.986 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 14.488 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 14.488 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK 1 CLK PIN_10 33 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 33; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "trafficlight.bdf" "" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/trafficlight.bdf" { { 776 240 408 792 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.430 ns) + CELL(0.720 ns) 2.280 ns fdiv1khz:inst12\|clk_out 2 REG LC_X8_Y6_N6 34 " "Info: 2: + IC(0.430 ns) + CELL(0.720 ns) = 2.280 ns; Loc. = LC_X8_Y6_N6; Fanout = 34; REG Node = 'fdiv1khz:inst12\|clk_out'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.150 ns" { CLK fdiv1khz:inst12|clk_out } "NODE_NAME" } } { "fdiv1khz.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/fdiv1khz.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.656 ns) + CELL(0.720 ns) 5.656 ns fdiv1hz:inst11\|clk_out 3 REG LC_X11_Y6_N6 14 " "Info: 3: + IC(2.656 ns) + CELL(0.720 ns) = 5.656 ns; Loc. = LC_X11_Y6_N6; Fanout = 14; REG Node = 'fdiv1hz:inst11\|clk_out'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.376 ns" { fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out } "NODE_NAME" } } { "fdiv1hz.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/fdiv1hz.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.997 ns) + CELL(0.720 ns) 9.373 ns counter05:inst1\|C_out 4 REG LC_X21_Y11_N4 1 " "Info: 4: + IC(2.997 ns) + CELL(0.720 ns) = 9.373 ns; Loc. = LC_X21_Y11_N4; Fanout = 1; REG Node = 'counter05:inst1\|C_out'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.717 ns" { fdiv1hz:inst11|clk_out counter05:inst1|C_out } "NODE_NAME" } } { "counter05.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter05.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.413 ns) + CELL(0.225 ns) 10.011 ns scan:inst\|EN_in 5 COMB LC_X21_Y11_N3 2 " "Info: 5: + IC(0.413 ns) + CELL(0.225 ns) = 10.011 ns; Loc. = LC_X21_Y11_N3; Fanout = 2; COMB Node = 'scan:inst\|EN_in'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.638 ns" { counter05:inst1|C_out scan:inst|EN_in } "NODE_NAME" } } { "scan.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/scan.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.930 ns) + CELL(0.547 ns) 14.488 ns scan:inst\|sdata\[0\] 6 REG LC_X21_Y11_N2 23 " "Info: 6: + IC(3.930 ns) + CELL(0.547 ns) = 14.488 ns; Loc. = LC_X21_Y11_N2; Fanout = 23; REG Node = 'scan:inst\|sdata\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.477 ns" { scan:inst|EN_in scan:inst|sdata[0] } "NODE_NAME" } } { "scan.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/scan.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.062 ns ( 28.04 % ) " "Info: Total cell delay = 4.062 ns ( 28.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.426 ns ( 71.96 % ) " "Info: Total interconnect delay = 10.426 ns ( 71.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.488 ns" { CLK fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter05:inst1|C_out scan:inst|EN_in scan:inst|sdata[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "14.488 ns" { CLK CLK~out0 fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter05:inst1|C_out scan:inst|EN_in scan:inst|sdata[0] } { 0.000ns 0.000ns 0.430ns 2.656ns 2.997ns 0.413ns 3.930ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.720ns 0.225ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "scan.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/scan.v" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.325 ns + Longest register pin " "Info: + Longest register to pin delay is 9.325 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns scan:inst\|sdata\[0\] 1 REG LC_X21_Y11_N2 23 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y11_N2; Fanout = 23; REG Node = 'scan:inst\|sdata\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { scan:inst|sdata[0] } "NODE_NAME" } } { "scan.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/scan.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.559 ns) + CELL(0.340 ns) 1.899 ns dispmux:inst8\|Selector0~214 2 COMB LC_X22_Y10_N2 3 " "Info: 2: + IC(1.559 ns) + CELL(0.340 ns) = 1.899 ns; Loc. = LC_X22_Y10_N2; Fanout = 3; COMB Node = 'dispmux:inst8\|Selector0~214'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.899 ns" { scan:inst|sdata[0] dispmux:inst8|Selector0~214 } "NODE_NAME" } } { "dispmux.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/dispmux.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.862 ns) + CELL(0.088 ns) 2.849 ns dispmux:inst8\|Selector0~216 3 COMB LC_X20_Y10_N0 1 " "Info: 3: + IC(0.862 ns) + CELL(0.088 ns) = 2.849 ns; Loc. = LC_X20_Y10_N0; Fanout = 1; COMB Node = 'dispmux:inst8\|Selector0~216'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.950 ns" { dispmux:inst8|Selector0~214 dispmux:inst8|Selector0~216 } "NODE_NAME" } } { "dispmux.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/dispmux.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.908 ns) + CELL(0.340 ns) 4.097 ns dispmux:inst8\|Selector2~79 4 COMB LC_X20_Y11_N1 1 " "Info: 4: + IC(0.908 ns) + CELL(0.340 ns) = 4.097 ns; Loc. = LC_X20_Y11_N1; Fanout = 1; COMB Node = 'dispmux:inst8\|Selector2~79'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.248 ns" { dispmux:inst8|Selector0~216 dispmux:inst8|Selector2~79 } "NODE_NAME" } } { "dispmux.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/dispmux.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.923 ns) + CELL(0.340 ns) 5.360 ns dispmux:inst8\|Selector2~80 5 COMB LC_X20_Y10_N9 7 " "Info: 5: + IC(0.923 ns) + CELL(0.340 ns) = 5.360 ns; Loc. = LC_X20_Y10_N9; Fanout = 7; COMB Node = 'dispmux:inst8\|Selector2~80'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.263 ns" { dispmux:inst8|Selector2~79 dispmux:inst8|Selector2~80 } "NODE_NAME" } } { "dispmux.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/dispmux.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.593 ns) + CELL(0.088 ns) 6.041 ns dispdecoder:inst7\|WideOr5~19 6 COMB LC_X19_Y10_N4 1 " "Info: 6: + IC(0.593 ns) + CELL(0.088 ns) = 6.041 ns; Loc. = LC_X19_Y10_N4; Fanout = 1; COMB Node = 'dispdecoder:inst7\|WideOr5~19'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.681 ns" { dispmux:inst8|Selector2~80 dispdecoder:inst7|WideOr5~19 } "NODE_NAME" } } { "dispdecoder.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/dispdecoder.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.650 ns) + CELL(1.634 ns) 9.325 ns SEG_Data\[2\] 7 PIN PIN_70 0 " "Info: 7: + IC(1.650 ns) + CELL(1.634 ns) = 9.325 ns; Loc. = PIN_70; Fanout = 0; PIN Node = 'SEG_Data\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.284 ns" { dispdecoder:inst7|WideOr5~19 SEG_Data[2] } "NODE_NAME" } } { "trafficlight.bdf" "" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/trafficlight.bdf" { { 760 784 960 776 "SEG_Data\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.830 ns ( 30.35 % ) " "Info: Total cell delay = 2.830 ns ( 30.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.495 ns ( 69.65 % ) " "Info: Total interconnect delay = 6.495 ns ( 69.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.325 ns" { scan:inst|sdata[0] dispmux:inst8|Selector0~214 dispmux:inst8|Selector0~216 dispmux:inst8|Selector2~79 dispmux:inst8|Selector2~80 dispdecoder:inst7|WideOr5~19 SEG_Data[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.325 ns" { scan:inst|sdata[0] dispmux:inst8|Selector0~214 dispmux:inst8|Selector0~216 dispmux:inst8|Selector2~79 dispmux:inst8|Selector2~80 dispdecoder:inst7|WideOr5~19 SEG_Data[2] } { 0.000ns 1.559ns 0.862ns 0.908ns 0.923ns 0.593ns 1.650ns } { 0.000ns 0.340ns 0.088ns 0.340ns 0.340ns 0.088ns 1.634ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.488 ns" { CLK fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter05:inst1|C_out scan:inst|EN_in scan:inst|sdata[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "14.488 ns" { CLK CLK~out0 fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter05:inst1|C_out scan:inst|EN_in scan:inst|sdata[0] } { 0.000ns 0.000ns 0.430ns 2.656ns 2.997ns 0.413ns 3.930ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.720ns 0.225ns 0.547ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.325 ns" { scan:inst|sdata[0] dispmux:inst8|Selector0~214 dispmux:inst8|Selector0~216 dispmux:inst8|Selector2~79 dispmux:inst8|Selector2~80 dispdecoder:inst7|WideOr5~19 SEG_Data[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.325 ns" { scan:inst|sdata[0] dispmux:inst8|Selector0~214 dispmux:inst8|Selector0~216 dispmux:inst8|Selector2~79 dispmux:inst8|Selector2~80 dispdecoder:inst7|WideOr5~19 SEG_Data[2] } { 0.000ns 1.559ns 0.862ns 0.908ns 0.923ns 0.593ns 1.650ns } { 0.000ns 0.340ns 0.088ns 0.340ns 0.340ns 0.088ns 1.634ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "SW Yellow2 9.004 ns Longest " "Info: Longest tpd from source pin \"SW\" to destination pin \"Yellow2\" is 9.004 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns SW 1 PIN PIN_73 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_73; Fanout = 6; PIN Node = 'SW'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SW } "NODE_NAME" } } { "trafficlight.bdf" "" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/trafficlight.bdf" { { 752 240 408 768 "SW" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.468 ns) + CELL(0.088 ns) 5.686 ns control:inst14\|Yellow2~13 2 COMB LC_X22_Y10_N9 1 " "Info: 2: + IC(4.468 ns) + CELL(0.088 ns) = 5.686 ns; Loc. = LC_X22_Y10_N9; Fanout = 1; COMB Node = 'control:inst14\|Yellow2~13'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.556 ns" { SW control:inst14|Yellow2~13 } "NODE_NAME" } } { "control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/control.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.696 ns) + CELL(1.622 ns) 9.004 ns Yellow2 3 PIN PIN_47 0 " "Info: 3: + IC(1.696 ns) + CELL(1.622 ns) = 9.004 ns; Loc. = PIN_47; Fanout = 0; PIN Node = 'Yellow2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.318 ns" { control:inst14|Yellow2~13 Yellow2 } "NODE_NAME" } } { "trafficlight.bdf" "" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/trafficlight.bdf" { { 704 784 960 720 "Yellow2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.840 ns ( 31.54 % ) " "Info: Total cell delay = 2.840 ns ( 31.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.164 ns ( 68.46 % ) " "Info: Total interconnect delay = 6.164 ns ( 68.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.004 ns" { SW control:inst14|Yellow2~13 Yellow2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.004 ns" { SW SW~out0 control:inst14|Yellow2~13 Yellow2 } { 0.000ns 0.000ns 4.468ns 1.696ns } { 0.000ns 1.130ns 0.088ns 1.622ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}