trafficlight.tan.qmsg

是一些很好的FPGA设计实例

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "trafficlight.bdf" "" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/trafficlight.bdf" { { 776 240 408 792 "CLK" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "5 " "Warning: Found 5 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "fdiv1hz:inst11\|clk_out " "Info: Detected ripple clock \"fdiv1hz:inst11\|clk_out\" as buffer" {  } { { "fdiv1hz.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/fdiv1hz.v" 3 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fdiv1hz:inst11\|clk_out" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fdiv1khz:inst12\|clk_out " "Info: Detected ripple clock \"fdiv1khz:inst12\|clk_out\" as buffer" {  } { { "fdiv1khz.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/fdiv1khz.v" 3 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fdiv1khz:inst12\|clk_out" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "counter55:inst2\|C_out " "Info: Detected ripple clock \"counter55:inst2\|C_out\" as buffer" {  } { { "counter55.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter55.v" 4 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "counter55:inst2\|C_out" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "counter05:inst1\|C_out " "Info: Detected ripple clock \"counter05:inst1\|C_out\" as buffer" {  } { { "counter05.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter05.v" 4 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "counter05:inst1\|C_out" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "scan:inst\|EN_in " "Info: Detected gated clock \"scan:inst\|EN_in\" as buffer" {  } { { "scan.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/scan.v" 9 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "scan:inst\|EN_in" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register scan:inst\|sdata\[0\] register counter55:inst2\|CData0\[3\] 143.08 MHz 6.989 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 143.08 MHz between source register \"scan:inst\|sdata\[0\]\" and destination register \"counter55:inst2\|CData0\[3\]\" (period= 6.989 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.499 ns + Longest register register " "Info: + Longest register to register delay is 1.499 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns scan:inst\|sdata\[0\] 1 REG LC_X21_Y11_N2 23 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y11_N2; Fanout = 23; REG Node = 'scan:inst\|sdata\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { scan:inst|sdata[0] } "NODE_NAME" } } { "scan.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/scan.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.461 ns) + CELL(0.225 ns) 0.686 ns counter55:inst2\|CData0~262 2 COMB LC_X21_Y11_N7 3 " "Info: 2: + IC(0.461 ns) + CELL(0.225 ns) = 0.686 ns; Loc. = LC_X21_Y11_N7; Fanout = 3; COMB Node = 'counter55:inst2\|CData0~262'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.686 ns" { scan:inst|sdata[0] counter55:inst2|CData0~262 } "NODE_NAME" } } { "counter55.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter55.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.575 ns) + CELL(0.238 ns) 1.499 ns counter55:inst2\|CData0\[3\] 3 REG LC_X22_Y11_N2 7 " "Info: 3: + IC(0.575 ns) + CELL(0.238 ns) = 1.499 ns; Loc. = LC_X22_Y11_N2; Fanout = 7; REG Node = 'counter55:inst2\|CData0\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.813 ns" { counter55:inst2|CData0~262 counter55:inst2|CData0[3] } "NODE_NAME" } } { "counter55.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter55.v" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.463 ns ( 30.89 % ) " "Info: Total cell delay = 0.463 ns ( 30.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.036 ns ( 69.11 % ) " "Info: Total interconnect delay = 1.036 ns ( 69.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.499 ns" { scan:inst|sdata[0] counter55:inst2|CData0~262 counter55:inst2|CData0[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.499 ns" { scan:inst|sdata[0] counter55:inst2|CData0~262 counter55:inst2|CData0[3] } { 0.000ns 0.461ns 0.575ns } { 0.000ns 0.225ns 0.238ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-5.288 ns - Smallest " "Info: - Smallest clock skew is -5.288 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 9.200 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 9.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK 1 CLK PIN_10 33 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 33; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "trafficlight.bdf" "" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/trafficlight.bdf" { { 776 240 408 792 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.430 ns) + CELL(0.720 ns) 2.280 ns fdiv1khz:inst12\|clk_out 2 REG LC_X8_Y6_N6 34 " "Info: 2: + IC(0.430 ns) + CELL(0.720 ns) = 2.280 ns; Loc. = LC_X8_Y6_N6; Fanout = 34; REG Node = 'fdiv1khz:inst12\|clk_out'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.150 ns" { CLK fdiv1khz:inst12|clk_out } "NODE_NAME" } } { "fdiv1khz.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/fdiv1khz.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.656 ns) + CELL(0.720 ns) 5.656 ns fdiv1hz:inst11\|clk_out 3 REG LC_X11_Y6_N6 14 " "Info: 3: + IC(2.656 ns) + CELL(0.720 ns) = 5.656 ns; Loc. = LC_X11_Y6_N6; Fanout = 14; REG Node = 'fdiv1hz:inst11\|clk_out'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.376 ns" { fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out } "NODE_NAME" } } { "fdiv1hz.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/fdiv1hz.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.997 ns) + CELL(0.547 ns) 9.200 ns counter55:inst2\|CData0\[3\] 4 REG LC_X22_Y11_N2 7 " "Info: 4: + IC(2.997 ns) + CELL(0.547 ns) = 9.200 ns; Loc. = LC_X22_Y11_N2; Fanout = 7; REG Node = 'counter55:inst2\|CData0\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.544 ns" { fdiv1hz:inst11|clk_out counter55:inst2|CData0[3] } "NODE_NAME" } } { "counter55.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter55.v" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.117 ns ( 33.88 % ) " "Info: Total cell delay = 3.117 ns ( 33.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.083 ns ( 66.12 % ) " "Info: Total interconnect delay = 6.083 ns ( 66.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.200 ns" { CLK fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter55:inst2|CData0[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.200 ns" { CLK CLK~out0 fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter55:inst2|CData0[3] } { 0.000ns 0.000ns 0.430ns 2.656ns 2.997ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 14.488 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 14.488 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK 1 CLK PIN_10 33 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 33; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "trafficlight.bdf" "" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/trafficlight.bdf" { { 776 240 408 792 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.430 ns) + CELL(0.720 ns) 2.280 ns fdiv1khz:inst12\|clk_out 2 REG LC_X8_Y6_N6 34 " "Info: 2: + IC(0.430 ns) + CELL(0.720 ns) = 2.280 ns; Loc. = LC_X8_Y6_N6; Fanout = 34; REG Node = 'fdiv1khz:inst12\|clk_out'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.150 ns" { CLK fdiv1khz:inst12|clk_out } "NODE_NAME" } } { "fdiv1khz.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/fdiv1khz.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.656 ns) + CELL(0.720 ns) 5.656 ns fdiv1hz:inst11\|clk_out 3 REG LC_X11_Y6_N6 14 " "Info: 3: + IC(2.656 ns) + CELL(0.720 ns) = 5.656 ns; Loc. = LC_X11_Y6_N6; Fanout = 14; REG Node = 'fdiv1hz:inst11\|clk_out'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.376 ns" { fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out } "NODE_NAME" } } { "fdiv1hz.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/fdiv1hz.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.997 ns) + CELL(0.720 ns) 9.373 ns counter05:inst1\|C_out 4 REG LC_X21_Y11_N4 1 " "Info: 4: + IC(2.997 ns) + CELL(0.720 ns) = 9.373 ns; Loc. = LC_X21_Y11_N4; Fanout = 1; REG Node = 'counter05:inst1\|C_out'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.717 ns" { fdiv1hz:inst11|clk_out counter05:inst1|C_out } "NODE_NAME" } } { "counter05.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter05.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.413 ns) + CELL(0.225 ns) 10.011 ns scan:inst\|EN_in 5 COMB LC_X21_Y11_N3 2 " "Info: 5: + IC(0.413 ns) + CELL(0.225 ns) = 10.011 ns; Loc. = LC_X21_Y11_N3; Fanout = 2; COMB Node = 'scan:inst\|EN_in'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.638 ns" { counter05:inst1|C_out scan:inst|EN_in } "NODE_NAME" } } { "scan.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/scan.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.930 ns) + CELL(0.547 ns) 14.488 ns scan:inst\|sdata\[0\] 6 REG LC_X21_Y11_N2 23 " "Info: 6: + IC(3.930 ns) + CELL(0.547 ns) = 14.488 ns; Loc. = LC_X21_Y11_N2; Fanout = 23; REG Node = 'scan:inst\|sdata\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.477 ns" { scan:inst|EN_in scan:inst|sdata[0] } "NODE_NAME" } } { "scan.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/scan.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.062 ns ( 28.04 % ) " "Info: Total cell delay = 4.062 ns ( 28.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.426 ns ( 71.96 % ) " "Info: Total interconnect delay = 10.426 ns ( 71.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.488 ns" { CLK fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter05:inst1|C_out scan:inst|EN_in scan:inst|sdata[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "14.488 ns" { CLK CLK~out0 fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter05:inst1|C_out scan:inst|EN_in scan:inst|sdata[0] } { 0.000ns 0.000ns 0.430ns 2.656ns 2.997ns 0.413ns 3.930ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.720ns 0.225ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.200 ns" { CLK fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter55:inst2|CData0[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.200 ns" { CLK CLK~out0 fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter55:inst2|CData0[3] } { 0.000ns 0.000ns 0.430ns 2.656ns 2.997ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.547ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.488 ns" { CLK fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter05:inst1|C_out scan:inst|EN_in scan:inst|sdata[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "14.488 ns" { CLK CLK~out0 fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter05:inst1|C_out scan:inst|EN_in scan:inst|sdata[0] } { 0.000ns 0.000ns 0.430ns 2.656ns 2.997ns 0.413ns 3.930ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.720ns 0.225ns 0.547ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "scan.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/scan.v" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "counter55.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter55.v" 53 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.499 ns" { scan:inst|sdata[0] counter55:inst2|CData0~262 counter55:inst2|CData0[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.499 ns" { scan:inst|sdata[0] counter55:inst2|CData0~262 counter55:inst2|CData0[3] } { 0.000ns 0.461ns 0.575ns } { 0.000ns 0.225ns 0.238ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.200 ns" { CLK fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter55:inst2|CData0[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.200 ns" { CLK CLK~out0 fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter55:inst2|CData0[3] } { 0.000ns 0.000ns 0.430ns 2.656ns 2.997ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.547ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.488 ns" { CLK fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter05:inst1|C_out scan:inst|EN_in scan:inst|sdata[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "14.488 ns" { CLK CLK~out0 fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter05:inst1|C_out scan:inst|EN_in scan:inst|sdata[0] } { 0.000ns 0.000ns 0.430ns 2.656ns 2.997ns 0.413ns 3.930ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.720ns 0.225ns 0.547ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}