trafficlight.map.qmsg

是一些很好的FPGA设计实例

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 counter55.v(42) " "Warning (10230): Verilog HDL assignment warning at counter55.v(42): truncated value with size 32 to match size of target (4)" {  } { { "counter55.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter55.v" 42 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 4 counter55.v(59) " "Warning (10230): Verilog HDL assignment warning at counter55.v(59): truncated value with size 8 to match size of target (4)" {  } { { "counter55.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter55.v" 59 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 4 counter55.v(61) " "Warning (10230): Verilog HDL assignment warning at counter55.v(61): truncated value with size 8 to match size of target (4)" {  } { { "counter55.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter55.v" 61 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 4 counter55.v(63) " "Warning (10230): Verilog HDL assignment warning at counter55.v(63): truncated value with size 8 to match size of target (4)" {  } { { "counter55.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter55.v" 63 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 4 counter55.v(65) " "Warning (10230): Verilog HDL assignment warning at counter55.v(65): truncated value with size 8 to match size of target (4)" {  } { { "counter55.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter55.v" 65 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fdiv1hz fdiv1hz:inst11 " "Info: Elaborating entity \"fdiv1hz\" for hierarchy \"fdiv1hz:inst11\"" {  } { { "trafficlight.bdf" "inst11" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/trafficlight.bdf" { { 568 296 416 664 "inst11" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fdiv1khz fdiv1khz:inst12 " "Info: Elaborating entity \"fdiv1khz\" for hierarchy \"fdiv1khz:inst12\"" {  } { { "trafficlight.bdf" "inst12" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/trafficlight.bdf" { { 568 440 560 664 "inst12" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "countersel countersel:inst3 " "Info: Elaborating entity \"countersel\" for hierarchy \"countersel:inst3\"" {  } { { "trafficlight.bdf" "inst3" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/trafficlight.bdf" { { 328 336 480 424 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter05 counter05:inst1 " "Info: Elaborating entity \"counter05\" for hierarchy \"counter05:inst1\"" {  } { { "trafficlight.bdf" "inst1" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/trafficlight.bdf" { { 112 336 496 208 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 counter05.v(32) " "Warning (10230): Verilog HDL assignment warning at counter05.v(32): truncated value with size 32 to match size of target (4)" {  } { { "counter05.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter05.v" 32 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 4 counter05.v(49) " "Warning (10230): Verilog HDL assignment warning at counter05.v(49): truncated value with size 8 to match size of target (4)" {  } { { "counter05.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter05.v" 49 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 4 counter05.v(51) " "Warning (10230): Verilog HDL assignment warning at counter05.v(51): truncated value with size 8 to match size of target (4)" {  } { { "counter05.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter05.v" 51 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dispdecoder dispdecoder:inst7 " "Info: Elaborating entity \"dispdecoder\" for hierarchy \"dispdecoder:inst7\"" {  } { { "trafficlight.bdf" "inst7" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/trafficlight.bdf" { { 424 832 928 608 "inst7" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dispmux dispmux:inst8 " "Info: Elaborating entity \"dispmux\" for hierarchy \"dispmux:inst8\"" {  } { { "trafficlight.bdf" "inst8" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/trafficlight.bdf" { { 312 752 928 408 "inst8" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "dispmux.v(14) " "Info (10264): Verilog HDL Case Statement information at dispmux.v(14): all case item expressions in this case statement are onehot" {  } { { "dispmux.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/dispmux.v" 14 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "datamux datamux:inst6 " "Info: Elaborating entity \"datamux\" for hierarchy \"datamux:inst6\"" {  } { { "trafficlight.bdf" "inst6" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/trafficlight.bdf" { { 160 736 912 288 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dispselect dispselect:inst9 " "Info: Elaborating entity \"dispselect\" for hierarchy \"dispselect:inst9\"" {  } { { "trafficlight.bdf" "inst9" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/trafficlight.bdf" { { 568 576 712 664 "inst9" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "counter05:inst1\|CData1\[0\] counter05:inst1\|CData1\[3\] " "Info: Duplicate register \"counter05:inst1\|CData1\[0\]\" merged to single register \"counter05:inst1\|CData1\[3\]\"" {  } { { "counter05.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter05.v" 42 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "counter05:inst1\|CData1\[2\] counter05:inst1\|CData1\[3\] " "Info: Duplicate register \"counter05:inst1\|CData1\[2\]\" merged to single register \"counter05:inst1\|CData1\[3\]\"" {  } { { "counter05.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter05.v" 42 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "counter05:inst1\|CData1\[1\] counter05:inst1\|CData1\[3\] " "Info: Duplicate register \"counter05:inst1\|CData1\[1\]\" merged to single register \"counter05:inst1\|CData1\[3\]\"" {  } { { "counter05.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter05.v" 42 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "counter05:inst1\|CData1\[3\] data_in GND " "Warning: Reduced register \"counter05:inst1\|CData1\[3\]\" with stuck data_in port to stuck value GND" {  } { { "counter05.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter05.v" 42 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "dispselect:inst9\|D_OUT\[1\] dispselect:inst9\|D_OUT\[0\] " "Info: Duplicate register \"dispselect:inst9\|D_OUT\[1\]\" merged to single register \"dispselect:inst9\|D_OUT\[0\]\", power-up level changed" {  } { { "dispselect.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/dispselect.v" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "SEG_Data\[0\] GND " "Warning: Pin \"SEG_Data\[0\]\" stuck at GND" {  } { { "trafficlight.bdf" "" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/trafficlight.bdf" { { 760 784 960 776 "SEG_Data\[7..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "179 " "Info: Implemented 179 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "160 " "Info: Implemented 160 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu May 22 20:57:22 2008 " "Info: Processing ended: Thu May 22 20:57:22 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/trafficlight.map.smsg " "Info: Generated suppressed messages file E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/trafficlight.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}