trafficlight.map.qmsg

是一些很好的FPGA设计实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 22 20:57:15 2008 " "Info: Processing started: Thu May 22 20:57:15 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off trafficlight -c trafficlight " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off trafficlight -c trafficlight" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "control.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file control.v" { { "Info" "ISGN_ENTITY_NAME" "1 control " "Info: Found entity 1: control" {  } { { "control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/control.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "counter05.v(20) " "Warning (10268): Verilog HDL information at counter05.v(20): Always Construct contains both blocking and non-blocking assignments" {  } { { "counter05.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter05.v" 20 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter05.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file counter05.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter05 " "Info: Found entity 1: counter05" {  } { { "counter05.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter05.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "counter55.v(19) " "Warning (10268): Verilog HDL information at counter55.v(19): Always Construct contains both blocking and non-blocking assignments" {  } { { "counter55.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter55.v" 19 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter55.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file counter55.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter55 " "Info: Found entity 1: counter55" {  } { { "counter55.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter55.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "countersel.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file countersel.v" { { "Info" "ISGN_ENTITY_NAME" "1 countersel " "Info: Found entity 1: countersel" {  } { { "countersel.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/countersel.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dataconvert05.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file dataconvert05.v" { { "Info" "ISGN_ENTITY_NAME" "1 dataconvert05 " "Info: Found entity 1: dataconvert05" {  } { { "dataconvert05.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/dataconvert05.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dataconvert55.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file dataconvert55.v" { { "Info" "ISGN_ENTITY_NAME" "1 dataconvert55 " "Info: Found entity 1: dataconvert55" {  } { { "dataconvert55.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/dataconvert55.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "datamux.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file datamux.v" { { "Info" "ISGN_ENTITY_NAME" "1 datamux " "Info: Found entity 1: datamux" {  } { { "datamux.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/datamux.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dispdecoder.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file dispdecoder.v" { { "Info" "ISGN_ENTITY_NAME" "1 dispdecoder " "Info: Found entity 1: dispdecoder" {  } { { "dispdecoder.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/dispdecoder.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dispmux.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file dispmux.v" { { "Info" "ISGN_ENTITY_NAME" "1 dispmux " "Info: Found entity 1: dispmux" {  } { { "dispmux.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/dispmux.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dispselect.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file dispselect.v" { { "Info" "ISGN_ENTITY_NAME" "1 dispselect " "Info: Found entity 1: dispselect" {  } { { "dispselect.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/dispselect.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "fdiv1hz.v(9) " "Warning (10268): Verilog HDL information at fdiv1hz.v(9): Always Construct contains both blocking and non-blocking assignments" {  } { { "fdiv1hz.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/fdiv1hz.v" 9 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fdiv1hz.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fdiv1hz.v" { { "Info" "ISGN_ENTITY_NAME" "1 fdiv1hz " "Info: Found entity 1: fdiv1hz" {  } { { "fdiv1hz.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/fdiv1hz.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "fdiv1khz.v(10) " "Warning (10268): Verilog HDL information at fdiv1khz.v(10): Always Construct contains both blocking and non-blocking assignments" {  } { { "fdiv1khz.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/fdiv1khz.v" 10 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fdiv1khz.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fdiv1khz.v" { { "Info" "ISGN_ENTITY_NAME" "1 fdiv1khz " "Info: Found entity 1: fdiv1khz" {  } { { "fdiv1khz.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/fdiv1khz.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "scan.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file scan.v" { { "Info" "ISGN_ENTITY_NAME" "1 scan " "Info: Found entity 1: scan" {  } { { "scan.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/scan.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "trafficlight.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file trafficlight.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 trafficlight " "Info: Found entity 1: trafficlight" {  } { { "trafficlight.bdf" "" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/trafficlight.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "trafficlight " "Info: Elaborating entity \"trafficlight\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control control:inst14 " "Info: Elaborating entity \"control\" for hierarchy \"control:inst14\"" {  } { { "trafficlight.bdf" "inst14" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/trafficlight.bdf" { { 384 528 672 544 "inst14" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scan scan:inst " "Info: Elaborating entity \"scan\" for hierarchy \"scan:inst\"" {  } { { "trafficlight.bdf" "inst" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/trafficlight.bdf" { { 440 344 488 536 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter55 counter55:inst2 " "Info: Elaborating entity \"counter55\" for hierarchy \"counter55:inst2\"" {  } { { "trafficlight.bdf" "inst2" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/trafficlight.bdf" { { 216 336 496 312 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 counter55.v(37) " "Warning (10230): Verilog HDL assignment warning at counter55.v(37): truncated value with size 32 to match size of target (4)" {  } { { "counter55.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/counter55.v" 37 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}