counter24.vhd

来自「是一些很好的FPGA设计实例」· VHDL 代码 · 共 32 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter24 is
    Port ( clk : in std_logic;     --时钟信号的输入端口
         preset : in std_logic;    --复位信号的输入
         din : in std_logic_vector(5 downto 0);   --六位二进制数据的输入
         dout : out std_logic_vector(7 downto 0));   --六位二进制数据的输出
end counter24;
architecture Behavioral of counter24 is
signal count : std_logic_vector(5 downto 0);    --定义一个六位的二进制数据信号
begin
    dout <= "00"&count;
	process(clk,preset,din)
	begin
	   if preset= '1' then    --复位有效时，数据初始化
		   count <= din;
       elsif rising_edge(clk) then	   --时钟上升沿执行then 后面的指令
		   if count(3 downto 0)>="1001" then   
			 count(3 downto 0)<="0000";   -- count的低四位计数到9时，清零
			count(5 downto 4)<=count(5 downto 4) +1;  -- count高两位加1
         else
			count(3 downto 0)<=count(3 downto 0)+1;  --否则，count的低四位加1
         end if;
		 if count="100011" then    
		   count<="000000";     --当count计数到24时，count清零
         end if;
      end if;
   end process;
end Behavioral;