dynamic_display.vhd

是一些很好的FPGA设计实例

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dynamic_display is
    Port ( clk : in std_logic;
           reset : in std_logic;
           hourh : in std_logic_vector(3 downto 0);
           hourl : in std_logic_vector(3 downto 0);
           minh : in std_logic_vector(3 downto 0);
           minl : in std_logic_vector(3 downto 0);
           secondh : in std_logic_vector(3 downto 0);
           secondl : in std_logic_vector(3 downto 0);
           select_dis : in std_logic;	--选择数码管显示的是小时和分钟还是分钟与秒钟
           cs : out std_logic_vector(1 downto 0);
           shift : out std_logic_vector(3 downto 0);
           data_led : out std_logic_vector(7 downto 0));
end dynamic_display;

architecture Behavioral of dynamic_display is
signal clk_shift: std_logic;
signal data_ledin : std_logic_vector (3 downto 0 );

begin
process (clk,reset)
variable cnt:integer range 0 to 50000;
  begin 
    if reset='1' then 
	   cnt:=0;
		elsif clk'event and clk='1' then
		   cnt:=cnt+1;
			if cnt=24999 then 
			   clk_shift<= not clk_shift;
				cnt:=0;
          end if;
      end if;
end process;

process (clk_shift,reset,select_dis)
variable cnt :std_logic_vector (1 downto 0);
begin 
if reset='1' then
   cnt:="00";
	cs<="11";
	shift<="1111";
	data_ledin<="1111";
   elsif clk_shift'event and clk_shift='1'  then
	        case cnt is
			     when "00"=> 
				   if select_dis='1' then
				          cs<="01";
				          shift<="1110";
				          data_ledin<=minh;
				          cnt:=cnt+1;
						else cs<="01";
				               shift<="1110";
				               data_ledin<=secondh;
				               cnt:=cnt+1;
 							end if;
			     when "01" =>
				   if select_dis='1' then
				      cs<="01";
				      shift<="1101";
				      data_ledin<=hourl;
						cnt:=cnt+1;
						else cs<="01";
				           shift<="1101";
				           data_ledin<=minl;
						     cnt:=cnt+1; 
							  end if;
				  when "10" =>
				   if select_dis='1' then
				      cs<="01";
				      shift<="1011";
				      data_ledin<=hourh;
						cnt:=cnt+1;
						else cs<="01";
				           shift<="1011";
				           data_ledin<=minh;
					    	  cnt:=cnt+1; 
							  end if;
					when "11" =>
					 if select_dis='1' then
					    cs<="01";
				       shift<="0111";
				       data_ledin<=minl;
						 cnt:="00";
						 else    cs<="01";
				             shift<="0111";
				             data_ledin<=secondl;
						       cnt:="00";
								 end if;
            	 when others=>
					    cs<="11";
                 	 shift<="1111";
	                data_ledin<="1111"; 
				end case;
			end if;
end process;
 process (data_ledin)               --译码
  begin
     case data_ledin is
         when"0000"=>data_led<="11000000";--0
	      when"0001"=>data_led<="11111001";--1
			when"0010"=>data_led<="10100100";--2
			when"0011"=>data_led<="10110000";--3
			when"0100"=>data_led<="10011001";--4
			when"0101"=>data_led<="10010010";--5
			when"0110"=>data_led<="10000010";--6
			when"0111"=>data_led<="11111000";--7
			when"1000"=>data_led<="10000000";--8
			when"1001"=>data_led<="10010000";--9
			when"1010"=>data_led<="11000000";
			when others=>data_led<="11111111";--No signal; 
       end case;

end process;



	   


end Behavioral;