lcd.syr

是一些很好的FPGA设计实例

---------------------------

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 1
# ROMs                                                 : 1
 13x8-bit ROM                                          : 1
# Adders/Subtractors                                   : 5
 10-bit adder                                          : 1
 19-bit adder                                          : 1
 4-bit adder                                           : 1
 9-bit adder                                           : 2
# Registers                                            : 85
 Flip-Flops                                            : 85
# Comparators                                          : 17
 10-bit comparator less                                : 12
 19-bit comparator greatequal                          : 1
 19-bit comparator less                                : 3
 9-bit comparator less                                 : 1
# Multiplexers                                         : 3
 9-bit 4-to-1 multiplexer                              : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1988 - Unit <LCD>: instances <Mcompar__n0015>, <Mcompar__n0116> of unit <LPM_COMPARE_1> and unit <LPM_COMPARE_15> are dual, second instance is removed

Optimizing unit <LCD> ...
Loading device for application Rf_Device from file '2s100e.nph' in environment D:\Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block LCD, actual ratio is 21.
FlipFlop cnt1_1_0 has been replicated 2 time(s)
FlipFlop cnt1_1_1 has been replicated 2 time(s)
FlipFlop cnt1_1_2 has been replicated 2 time(s)
FlipFlop cnt1_1_3 has been replicated 2 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : LCD.ngr
Top Level Output File Name         : LCD
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 23

Cell Usage :
# BELS                             : 515
#      GND                         : 1
#      INV                         : 6
#      LUT1                        : 1
#      LUT1_L                      : 24
#      LUT2                        : 21
#      LUT2_D                      : 7
#      LUT2_L                      : 7
#      LUT3                        : 67
#      LUT3_D                      : 9
#      LUT3_L                      : 14
#      LUT4                        : 162
#      LUT4_D                      : 26
#      LUT4_L                      : 101
#      MUXCY                       : 39
#      MUXF5                       : 11
#      VCC                         : 1
#      XORCY                       : 18
# FlipFlops/Latches                : 93
#      FD                          : 8
#      FDE                         : 10
#      FDR                         : 51
#      FDRE                        : 10
#      FDRS                        : 13
#      FDS                         : 1
# Clock Buffers                    : 2
#      BUFG                        : 1
#      BUFGP                       : 1
# IO Buffers                       : 22
#      IBUF                        : 1
#      OBUF                        : 21
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100epq208-7 

 Number of Slices:                     246  out of   1200    20%  
 Number of Slice Flip Flops:            93  out of   2400     3%  
 Number of 4 input LUTs:               439  out of   2400    18%  
 Number of bonded IOBs:                 23  out of    146    15%  
 Number of GCLKs:                        2  out of      4    50%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 10    |
clk_100k1                          | BUFG                   | 83    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -7

   Minimum period: 15.814ns (Maximum Frequency: 63.235MHz)
   Minimum input arrival time before clock: 7.741ns
   Maximum output required time after clock: 6.680ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 9.272ns (frequency: 107.852MHz)
  Total number of paths / destination ports: 112 / 10
-------------------------------------------------------------------------
Delay:               9.272ns (Levels of Logic = 5)
  Source:            cnt_0 (FF)
  Destination:       cnt_5 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: cnt_0 to cnt_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              9   0.886   1.935  cnt_0 (cnt_0)
     LUT2:I0->O            5   0.418   1.548  Ker3511 (N351)
     LUT4:I3->O            3   0.418   1.188  Ker721 (N72)
     LUT4:I3->O            2   0.418   1.035  Ker551 (N55)
     LUT3:I2->O            1   0.418   0.000  _n0000<5>_G (N2234)
     MUXF5:I1->O           1   0.360   0.000  _n0000<5> (_n0000<5>)
     FD:D                      0.648          cnt_5
    ----------------------------------------
    Total                      9.272ns (3.566ns logic, 5.706ns route)
                                       (38.5% logic, 61.5% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk_100k1'
  Clock period: 15.814ns (frequency: 63.235MHz)
  Total number of paths / destination ports: 14311 / 106
-------------------------------------------------------------------------
Delay:               15.814ns (Levels of Logic = 7)
  Source:            cnt1_1_6 (FF)
  Destination:       data_cnt_8 (FF)
  Source Clock:      clk_100k1 rising
  Destination Clock: clk_100k1 rising

  Data Path: cnt1_1_6 to data_cnt_8
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             12   0.886   2.205  cnt1_1_6 (cnt1_1_6)
     LUT2_L:I1->LO         1   0.418   0.100  Ker116_SW0 (N1898)
     LUT4:I3->O           17   0.418   2.565  Ker116 (N116)
     LUT4:I0->O           19   0.418   2.655  _n006321 (_n0063)
     LUT2:I1->O            8   0.418   1.845  Ker821 (N82)
     LUT4_L:I0->LO         1   0.418   0.100  Ker49 (Ker4_map350)
     LUT4:I0->O            3   0.418   1.188  Ker466 (N41)
     LUT4:I3->O            1   0.418   0.828  _n0046<8>29 (N1954)
     FDRS:S                    0.516          data_cnt_8
    ----------------------------------------
    Total                     15.814ns (4.328ns logic, 11.486ns route)
                                       (27.4% logic, 72.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk_100k1'
  Total number of paths / destination ports: 83 / 83
-------------------------------------------------------------------------
Offset:              7.741ns (Levels of Logic = 2)
  Source:            rst (PAD)
  Destination:       cd (FF)
  Destination Clock: clk_100k1 rising

  Data Path: rst to cd
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            74   0.769   3.915  rst_IBUF (rst_IBUF)
     INV:I->O             10   0.418   2.025  rst_INV1_INV_0 (rst_INV)
     FDE:CE                    0.614          cd
    ----------------------------------------
    Total                      7.741ns (1.801ns logic, 5.940ns route)
                                       (23.3% logic, 76.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk_100k1'
  Total number of paths / destination ports: 18 / 18
-------------------------------------------------------------------------
Offset:              6.680ns (Levels of Logic = 1)
  Source:            wr (FF)
  Destination:       wr (PAD)
  Source Clock:      clk_100k1 rising

  Data Path: wr to wr
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              4   0.886   1.368  wr (wr_OBUF)
     OBUF:I->O                 4.426          wr_OBUF (wr)
    ----------------------------------------
    Total                      6.680ns (5.312ns logic, 1.368ns route)
                                       (79.5% logic, 20.5% route)

=========================================================================
CPU : 111.77 / 116.36 s | Elapsed : 112.00 / 116.00 s
 
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Total memory usage is 108200 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    2 (   0 filtered)