lcd.syr

是一些很好的FPGA设计实例

Release 8.1i - xst I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.01 / 3.34 s | Elapsed : 0.00 / 3.00 s
 
--> Parameter xsthdpdir set to ./xst
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--> Reading design: LCD.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
     5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "LCD.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "LCD"
Output Format                      : NGC
Target Device                      : xc2s100e-7-pq208

---- Source Options
Top Module Name                    : LCD
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : LCD.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/TMX_VHDL/lcd240128_ok/LCD.vhd" in Library work.
Architecture behavioral of Entity lcd is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <LCD> (Architecture <behavioral>).
INFO:Xst:1304 - Contents of register <rd> in unit <LCD> never changes during circuit operation. The register is replaced by logic.
Entity <LCD> analyzed. Unit <LCD> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <LCD>.
    Related source file is "E:/TMX_VHDL/lcd240128_ok/LCD.vhd".
    Found finite state machine <FSM_0> for signal <current_s>.
    -----------------------------------------------------------------------
    | States             | 16                                             |
    | Transitions        | 38                                             |
    | Inputs             | 8                                              |
    | Outputs            | 16                                             |
    | Clock              | clk_100k (rising_edge)                         |
    | Reset              | rst (positive)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | s0                                             |
    | Power Up State     | s0                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 13x8-bit ROM for signal <$n0004> created at line 133.
    Found 1-bit register for signal <s0_a>.
    Found 1-bit register for signal <s1_a>.
    Found 1-bit register for signal <s2_a>.
    Found 1-bit register for signal <s3_a>.
    Found 1-bit register for signal <s4_a>.
    Found 1-bit register for signal <s5_a>.
    Found 1-bit register for signal <s6_a>.
    Found 1-bit register for signal <wr>.
    Found 1-bit register for signal <cd>.
    Found 1-bit register for signal <lcd_rst>.
    Found 8-bit register for signal <lcd_data>.
    Found 9-bit 4-to-1 multiplexer for signal <$n0007>.
    Found 9-bit 4-to-1 multiplexer for signal <$n0009>.
    Found 9-bit 4-to-1 multiplexer for signal <$n0012>.
    Found 19-bit comparator less for signal <$n0014> created at line 111.
    Found 19-bit comparator less for signal <$n0015> created at line 112.
    Found 9-bit comparator less for signal <$n0052> created at line 72.
    Found 19-bit adder for signal <$n0055> created at line 174.
    Found 10-bit adder for signal <$n0056> created at line 171.
    Found 9-bit adder for signal <$n0057> created at line 420.
    Found 4-bit adder for signal <$n0058> created at line 105.
    Found 9-bit adder for signal <$n0059> created at line 68.
    Found 10-bit comparator less for signal <$n0063> created at line 294.
    Found 10-bit comparator less for signal <$n0064> created at line 295.
    Found 19-bit comparator less for signal <$n0081> created at line 129.
    Found 10-bit comparator less for signal <$n0082> created at line 135.
    Found 10-bit comparator less for signal <$n0083> created at line 138.
    Found 10-bit comparator less for signal <$n0084> created at line 140.
    Found 10-bit comparator less for signal <$n0085> created at line 144.
    Found 10-bit comparator less for signal <$n0086> created at line 148.
    Found 10-bit comparator less for signal <$n0087> created at line 151.
    Found 10-bit comparator less for signal <$n0088> created at line 153.
    Found 10-bit comparator less for signal <$n0089> created at line 157.
    Found 19-bit comparator greatequal for signal <$n0116> created at line 112.
    Found 10-bit comparator less for signal <$n0117> created at line 161.
    Found 10-bit comparator less for signal <$n0118> created at line 164.
    Found 1-bit register for signal <clk_100k>.
    Found 9-bit register for signal <cnt>.
    Found 19-bit register for signal <cnt1>.
    Found 10-bit register for signal <cnt1_1>.
    Found 4-bit register for signal <code_cnt>.
    Found 9-bit register for signal <data_cnt>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 ROM(s).
	inferred  70 D-type flip-flop(s).
	inferred   5 Adder/Subtractor(s).
	inferred  17 Comparator(s).
	inferred  27 Multiplexer(s).
Unit <LCD> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 1
 13x8-bit ROM                                          : 1
# Adders/Subtractors                                   : 5
 10-bit adder                                          : 1
 19-bit adder                                          : 1
 4-bit adder                                           : 1
 9-bit adder                                           : 2
# Registers                                            : 17
 1-bit register                                        : 11
 10-bit register                                       : 1
 19-bit register                                       : 1
 4-bit register                                        : 1
 8-bit register                                        : 1
 9-bit register                                        : 2
# Comparators                                          : 17
 10-bit comparator less                                : 12
 19-bit comparator greatequal                          : 1
 19-bit comparator less                                : 3
 9-bit comparator less                                 : 1
# Multiplexers                                         : 3
 9-bit 4-to-1 multiplexer                              : 3

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <current_s> on signal <current_s[1:16]> with speed1 encoding.
---------------------------
 State | Encoding
---------------------------
 s0    | 1000000000000000
 s1    | 0100000000000000
 s2    | 0010000000000000
 s3    | 0001000000000000
 s4    | 0000100000000000
 s5    | 0000010000000000
 s6    | 0000001000000000
 s7    | 0000000100000000
 s8    | 0000000010000000
 s9    | 0000000001000000
 s10   | 0000000000100000
 s11   | 0000000000010000
 s12   | 0000000000001000
 s13   | 0000000000000100
 s14   | 0000000000000010
 s15   | 0000000000000001