yellowflash.vhd

来自「是一些很好的FPGA设计实例」· VHDL 代码 · 共 22 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 --实现黄灯闪烁
entity yellowflash is
    Port ( f_1hz : in std_logic;
	        in_yellow:in std_logic;
           out_yellow : out std_logic);
end yellowflash;
architecture Behavioral of yellowflash is
begin
      process(f_1hz,in_yellow)
		begin
	       if in_yellow='0'then
	         out_yellow<=f_1hz;
		   else
		      out_yellow<='1';
		   end if;
		end process;
end Behavioral;