decoder.vhd

来自「是一些很好的FPGA设计实例」· VHDL 代码 · 共 49 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder is
   Port (din  :in  std_logic_vector(3 downto 0);  --需要显示的数据输入
         dout :out std_logic_vector(7 downto 0)); --译成相应的七段码的输出
end decoder;
architecture Behavioral of decoder is
begin
process(din)
begin
case din is
    when "0000" =>
                  dout<="10000001";	 --0
                 
    when "0001" =>
                  dout<="11001111";	  --1
                 
    when "0010" =>
                  dout<="10010010";	  --2 
                 
    when "0011" =>
                  dout<="10000110";	 --3
                  
    when "0100" =>
                  dout<="11001100";	  --4 
                 
    when "0101" =>
                  dout<="10100100";	  --5
                  
	 when "0110" =>
	               dout<="10100000";	  --6
                 
    when "0111" =>
                  dout<="10001111";	  --7
                  
    when "1000" =>
                  dout<="10000000";	  --8
                  
    when "1001" =>
                  dout<="10000100";	  --9
                 
	 when others =>
	               dout<="11111111";
                 end case;
end process;
end Behavioral;