div_50.vhd

来自「是一些很好的FPGA设计实例」· VHDL 代码 · 共 29 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- 50分频；

entity div_50 is
    Port (iclk : in  std_logic;
	       oclk : out std_logic);
end div_50;

architecture Behavioral of div_50 is

begin

process(iclk)
variable cnt : integer range 0 to 50;
begin
   if iclk'event and iclk='1' then cnt:=cnt+1;
	   if cnt<25 then oclk<='0';
		elsif cnt<50 then oclk<='1';
		else cnt:=0;oclk<='1';
		end if;
   end if;
end process;

end Behavioral;