div_10.vhd

来自「是一些很好的FPGA设计实例」· VHDL 代码 · 共 30 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  10分频；

entity div_10 is
    Port (iclk : in std_logic;
	       oclk : out std_logic );
end div_10;

architecture Behavioral of div_10 is

begin

process(iclk)													--40%的占空比；
variable cnt : std_logic_vector(3 downto 0);
begin
   if rising_edge(iclk) then
	   if cnt<"1001" then cnt:=cnt+1;
		else cnt:="0000";
		end if;
   end if;
   
	oclk<=cnt(2);
end process;

end Behavioral;