simple_fsm.tan.qmsg

是一些很好的FPGA设计实例

{ "Info" "ITDB_FULL_TPD_RESULT" "b x 8.381 ns Shortest " "Info: Shortest tpd from source pin b to destination pin x is 8.381 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns b 1 PIN PIN_C9 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_C9; Fanout = 1; PIN Node = 'b'" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "" { b } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.698 ns) + CELL(0.075 ns) 4.860 ns x~8 2 COMB LC_X36_Y30_N2 1 " "Info: 2: + IC(3.698 ns) + CELL(0.075 ns) = 4.860 ns; Loc. = LC_X36_Y30_N2; Fanout = 1; COMB Node = 'x~8'" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "3.773 ns" { b x~8 } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.117 ns) + CELL(2.404 ns) 8.381 ns x 3 PIN PIN_E9 0 " "Info: 3: + IC(1.117 ns) + CELL(2.404 ns) = 8.381 ns; Loc. = PIN_E9; Fanout = 0; PIN Node = 'x'" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "3.521 ns" { x~8 x } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.566 ns 42.55 % " "Info: Total cell delay = 3.566 ns ( 42.55 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.815 ns 57.45 % " "Info: Total interconnect delay = 4.815 ns ( 57.45 % )" {  } {  } 0}  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "8.381 ns" { b x~8 x } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu May 17 11:46:18 2007 " "Info: Processing ended: Thu May 17 11:46:18 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}