simple_fsm.tan.qmsg

是一些很好的FPGA设计实例

{ "Info" "ITDB_TSU_RESULT" "pr_state d clk 2.682 ns register " "Info: tsu for register pr_state (data pin = d, clock pin = clk) is 2.682 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.452 ns + Longest pin register " "Info: + Longest pin to register delay is 5.452 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns d 1 PIN PIN_D9 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_D9; Fanout = 1; PIN Node = 'd'" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "" { d } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.660 ns) + CELL(0.705 ns) 5.452 ns pr_state 2 REG LC_X36_Y30_N4 2 " "Info: 2: + IC(3.660 ns) + CELL(0.705 ns) = 5.452 ns; Loc. = LC_X36_Y30_N4; Fanout = 2; REG Node = 'pr_state'" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "4.365 ns" { d pr_state } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.792 ns 32.87 % " "Info: Total cell delay = 1.792 ns ( 32.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.660 ns 67.13 % " "Info: Total interconnect delay = 3.660 ns ( 67.13 % )" {  } {  } 0}  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "5.452 ns" { d pr_state } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.780 ns - Shortest register " "Info: - Shortest clock path from clock clk to destination register is 2.780 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns clk 1 CLK PIN_L7 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_L7; Fanout = 1; CLK Node = 'clk'" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.151 ns) + CELL(0.542 ns) 2.780 ns pr_state 2 REG LC_X36_Y30_N4 2 " "Info: 2: + IC(1.151 ns) + CELL(0.542 ns) = 2.780 ns; Loc. = LC_X36_Y30_N4; Fanout = 2; REG Node = 'pr_state'" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "1.693 ns" { clk pr_state } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.629 ns 58.60 % " "Info: Total cell delay = 1.629 ns ( 58.60 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.151 ns 41.40 % " "Info: Total interconnect delay = 1.151 ns ( 41.40 % )" {  } {  } 0}  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "2.780 ns" { clk pr_state } "NODE_NAME" } } }  } 0}  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "5.452 ns" { d pr_state } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "2.780 ns" { clk pr_state } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk x pr_state 7.230 ns register " "Info: tco from clock clk to destination pin x through register pr_state is 7.230 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.780 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 2.780 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns clk 1 CLK PIN_L7 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_L7; Fanout = 1; CLK Node = 'clk'" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.151 ns) + CELL(0.542 ns) 2.780 ns pr_state 2 REG LC_X36_Y30_N4 2 " "Info: 2: + IC(1.151 ns) + CELL(0.542 ns) = 2.780 ns; Loc. = LC_X36_Y30_N4; Fanout = 2; REG Node = 'pr_state'" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "1.693 ns" { clk pr_state } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.629 ns 58.60 % " "Info: Total cell delay = 1.629 ns ( 58.60 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.151 ns 41.40 % " "Info: Total interconnect delay = 1.151 ns ( 41.40 % )" {  } {  } 0}  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "2.780 ns" { clk pr_state } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.294 ns + Longest register pin " "Info: + Longest register to pin delay is 4.294 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pr_state 1 REG LC_X36_Y30_N4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X36_Y30_N4; Fanout = 2; REG Node = 'pr_state'" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "" { pr_state } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.407 ns) + CELL(0.366 ns) 0.773 ns x~8 2 COMB LC_X36_Y30_N2 1 " "Info: 2: + IC(0.407 ns) + CELL(0.366 ns) = 0.773 ns; Loc. = LC_X36_Y30_N2; Fanout = 1; COMB Node = 'x~8'" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "0.773 ns" { pr_state x~8 } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.117 ns) + CELL(2.404 ns) 4.294 ns x 3 PIN PIN_E9 0 " "Info: 3: + IC(1.117 ns) + CELL(2.404 ns) = 4.294 ns; Loc. = PIN_E9; Fanout = 0; PIN Node = 'x'" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "3.521 ns" { x~8 x } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.770 ns 64.51 % " "Info: Total cell delay = 2.770 ns ( 64.51 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.524 ns 35.49 % " "Info: Total interconnect delay = 1.524 ns ( 35.49 % )" {  } {  } 0}  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "4.294 ns" { pr_state x~8 x } "NODE_NAME" } } }  } 0}  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "2.780 ns" { clk pr_state } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "4.294 ns" { pr_state x~8 x } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "a x 8.473 ns Longest " "Info: Longest tpd from source pin a to destination pin x is 8.473 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns a 1 PIN PIN_B8 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_B8; Fanout = 1; PIN Node = 'a'" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "" { a } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.682 ns) + CELL(0.183 ns) 4.952 ns x~8 2 COMB LC_X36_Y30_N2 1 " "Info: 2: + IC(3.682 ns) + CELL(0.183 ns) = 4.952 ns; Loc. = LC_X36_Y30_N2; Fanout = 1; COMB Node = 'x~8'" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "3.865 ns" { a x~8 } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.117 ns) + CELL(2.404 ns) 8.473 ns x 3 PIN PIN_E9 0 " "Info: 3: + IC(1.117 ns) + CELL(2.404 ns) = 8.473 ns; Loc. = PIN_E9; Fanout = 0; PIN Node = 'x'" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "3.521 ns" { x~8 x } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.674 ns 43.36 % " "Info: Total cell delay = 3.674 ns ( 43.36 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.799 ns 56.64 % " "Info: Total interconnect delay = 4.799 ns ( 56.64 % )" {  } {  } 0}  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "8.473 ns" { a x~8 x } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "pr_state d clk -2.572 ns register " "Info: th for register pr_state (data pin = d, clock pin = clk) is -2.572 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.780 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 2.780 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns clk 1 CLK PIN_L7 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_L7; Fanout = 1; CLK Node = 'clk'" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.151 ns) + CELL(0.542 ns) 2.780 ns pr_state 2 REG LC_X36_Y30_N4 2 " "Info: 2: + IC(1.151 ns) + CELL(0.542 ns) = 2.780 ns; Loc. = LC_X36_Y30_N4; Fanout = 2; REG Node = 'pr_state'" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "1.693 ns" { clk pr_state } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.629 ns 58.60 % " "Info: Total cell delay = 1.629 ns ( 58.60 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.151 ns 41.40 % " "Info: Total interconnect delay = 1.151 ns ( 41.40 % )" {  } {  } 0}  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "2.780 ns" { clk pr_state } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.452 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.452 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns d 1 PIN PIN_D9 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_D9; Fanout = 1; PIN Node = 'd'" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "" { d } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.660 ns) + CELL(0.705 ns) 5.452 ns pr_state 2 REG LC_X36_Y30_N4 2 " "Info: 2: + IC(3.660 ns) + CELL(0.705 ns) = 5.452 ns; Loc. = LC_X36_Y30_N4; Fanout = 2; REG Node = 'pr_state'" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "4.365 ns" { d pr_state } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.792 ns 32.87 % " "Info: Total cell delay = 1.792 ns ( 32.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.660 ns 67.13 % " "Info: Total interconnect delay = 3.660 ns ( 67.13 % )" {  } {  } 0}  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "5.452 ns" { d pr_state } "NODE_NAME" } } }  } 0}  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "2.780 ns" { clk pr_state } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "5.452 ns" { d pr_state } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk x pr_state 7.230 ns register " "Info: Minimum tco from clock clk to destination pin x through register pr_state is 7.230 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.780 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 2.780 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns clk 1 CLK PIN_L7 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_L7; Fanout = 1; CLK Node = 'clk'" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.151 ns) + CELL(0.542 ns) 2.780 ns pr_state 2 REG LC_X36_Y30_N4 2 " "Info: 2: + IC(1.151 ns) + CELL(0.542 ns) = 2.780 ns; Loc. = LC_X36_Y30_N4; Fanout = 2; REG Node = 'pr_state'" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "1.693 ns" { clk pr_state } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.629 ns 58.60 % " "Info: Total cell delay = 1.629 ns ( 58.60 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.151 ns 41.40 % " "Info: Total interconnect delay = 1.151 ns ( 41.40 % )" {  } {  } 0}  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "2.780 ns" { clk pr_state } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.294 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.294 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pr_state 1 REG LC_X36_Y30_N4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X36_Y30_N4; Fanout = 2; REG Node = 'pr_state'" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "" { pr_state } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.407 ns) + CELL(0.366 ns) 0.773 ns x~8 2 COMB LC_X36_Y30_N2 1 " "Info: 2: + IC(0.407 ns) + CELL(0.366 ns) = 0.773 ns; Loc. = LC_X36_Y30_N2; Fanout = 1; COMB Node = 'x~8'" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "0.773 ns" { pr_state x~8 } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.117 ns) + CELL(2.404 ns) 4.294 ns x 3 PIN PIN_E9 0 " "Info: 3: + IC(1.117 ns) + CELL(2.404 ns) = 4.294 ns; Loc. = PIN_E9; Fanout = 0; PIN Node = 'x'" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "3.521 ns" { x~8 x } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.770 ns 64.51 % " "Info: Total cell delay = 2.770 ns ( 64.51 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.524 ns 35.49 % " "Info: Total interconnect delay = 1.524 ns ( 35.49 % )" {  } {  } 0}  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "4.294 ns" { pr_state x~8 x } "NODE_NAME" } } }  } 0}  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "2.780 ns" { clk pr_state } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "4.294 ns" { pr_state x~8 x } "NODE_NAME" } } }  } 0}