simple_fsm.tan.qmsg

是一些很好的FPGA设计实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 17 11:46:17 2007 " "Info: Processing started: Thu May 17 11:46:17 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off simple_fsm -c simple_fsm --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off simple_fsm -c simple_fsm --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 5 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register pr_state pr_state 422.12 MHz Internal " "Info: Clock clk Internal fmax is restricted to 422.12 MHz between source register pr_state and destination register pr_state" { { "Info" "ITDB_CLOCK_RATE" "clock 2.369 ns " "Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.616 ns + Longest register register " "Info: + Longest register to register delay is 0.616 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pr_state 1 REG LC_X36_Y30_N4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X36_Y30_N4; Fanout = 2; REG Node = 'pr_state'" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "" { pr_state } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.393 ns) + CELL(0.223 ns) 0.616 ns pr_state 2 REG LC_X36_Y30_N4 2 " "Info: 2: + IC(0.393 ns) + CELL(0.223 ns) = 0.616 ns; Loc. = LC_X36_Y30_N4; Fanout = 2; REG Node = 'pr_state'" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "0.616 ns" { pr_state pr_state } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.223 ns 36.20 % " "Info: Total cell delay = 0.223 ns ( 36.20 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.393 ns 63.80 % " "Info: Total interconnect delay = 0.393 ns ( 63.80 % )" {  } {  } 0}  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "0.616 ns" { pr_state pr_state } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.780 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 2.780 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns clk 1 CLK PIN_L7 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_L7; Fanout = 1; CLK Node = 'clk'" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.151 ns) + CELL(0.542 ns) 2.780 ns pr_state 2 REG LC_X36_Y30_N4 2 " "Info: 2: + IC(1.151 ns) + CELL(0.542 ns) = 2.780 ns; Loc. = LC_X36_Y30_N4; Fanout = 2; REG Node = 'pr_state'" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "1.693 ns" { clk pr_state } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.629 ns 58.60 % " "Info: Total cell delay = 1.629 ns ( 58.60 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.151 ns 41.40 % " "Info: Total interconnect delay = 1.151 ns ( 41.40 % )" {  } {  } 0}  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "2.780 ns" { clk pr_state } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.780 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 2.780 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns clk 1 CLK PIN_L7 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_L7; Fanout = 1; CLK Node = 'clk'" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.151 ns) + CELL(0.542 ns) 2.780 ns pr_state 2 REG LC_X36_Y30_N4 2 " "Info: 2: + IC(1.151 ns) + CELL(0.542 ns) = 2.780 ns; Loc. = LC_X36_Y30_N4; Fanout = 2; REG Node = 'pr_state'" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "1.693 ns" { clk pr_state } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.629 ns 58.60 % " "Info: Total cell delay = 1.629 ns ( 58.60 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.151 ns 41.40 % " "Info: Total interconnect delay = 1.151 ns ( 41.40 % )" {  } {  } 0}  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "2.780 ns" { clk pr_state } "NODE_NAME" } } }  } 0}  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "2.780 ns" { clk pr_state } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "2.780 ns" { clk pr_state } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 16 -1 0 } }  } 0}  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "0.616 ns" { pr_state pr_state } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "2.780 ns" { clk pr_state } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "2.780 ns" { clk pr_state } "NODE_NAME" } } }  } 0}  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/db/simple_fsm.quartus_db" { Floorplan "" "" "" { pr_state } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 16 -1 0 } }  } 0}