simple_fsm.map.qmsg

是一些很好的FPGA设计实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 17 11:44:30 2007 " "Info: Processing started: Thu May 17 11:44:30 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off simple_fsm -c simple_fsm " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off simple_fsm -c simple_fsm" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "simple_fsm.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file simple_fsm.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 simple_fsm-simple_fsm " "Info: Found design unit 1: simple_fsm-simple_fsm" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "simple_fsm-simple_fsm" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 simple_fsm " "Info: Found entity 1: simple_fsm" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "simple_fsm" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "c " "Warning: No output dependent on input pin c" {  } { { "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" "" "" { Text "D:/VHDL数字逻辑教程/8.2 简单的fsm#1/simple_fsm.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "9 " "Info: Implemented 9 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "6 " "Info: Implemented 6 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "2 " "Info: Implemented 2 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu May 17 11:44:35 2007 " "Info: Processing ended: Thu May 17 11:44:35 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}