parity_det.map.qmsg

来自「是一些很好的FPGA设计实例」· QMSG 代码 · 共 5 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 15 16:03:48 2007 " "Info: Processing started: Tue May 15 16:03:48 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off parity_det -c parity_det --generate_symbol=D:\\VHDL数字逻辑教程\\4.2通用奇偶校验检测器电路\\parity_det.vhd " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off parity_det -c parity_det --generate_symbol=D:\\VHDL数字逻辑教程\\4.2通用奇偶校验检测器电路\\parity_det.vhd" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue May 15 16:03:51 2007 " "Info: Processing ended: Tue May 15 16:03:51 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}