fuyongqi.tan.qmsg

是一些很好的FPGA设计实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 12 16:20:27 2007 " "Info: Processing started: Sat May 12 16:20:27 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off fuyongqi -c fuyongqi --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off fuyongqi -c fuyongqi --timing_analysis_only" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "s0 y 9.282 ns Longest " "Info: Longest tpd from source pin s0 to destination pin y is 9.282 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns s0 1 PIN PIN_AA2 2 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_AA2; Fanout = 2; PIN Node = 's0'" {  } { { "d:/vhdl数字逻辑教程/5.1多路复用器#1/db/fuyongqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.1多路复用器#1/db/fuyongqi_cmp.qrpt" Compiler "fuyongqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.1多路复用器#1/db/fuyongqi.quartus_db" { Floorplan "" "" "" { s0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.1多路复用器#1/fuyongqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.1多路复用器#1/fuyongqi.vhd" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.709 ns) + CELL(0.280 ns) 5.076 ns y~107 2 COMB LC_X52_Y1_N2 1 " "Info: 2: + IC(3.709 ns) + CELL(0.280 ns) = 5.076 ns; Loc. = LC_X52_Y1_N2; Fanout = 1; COMB Node = 'y~107'" {  } { { "d:/vhdl数字逻辑教程/5.1多路复用器#1/db/fuyongqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.1多路复用器#1/db/fuyongqi_cmp.qrpt" Compiler "fuyongqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.1多路复用器#1/db/fuyongqi.quartus_db" { Floorplan "" "" "3.989 ns" { s0 y~107 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.1多路复用器#1/fuyongqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.1多路复用器#1/fuyongqi.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.322 ns) + CELL(0.366 ns) 5.764 ns y~108 3 COMB LC_X52_Y1_N4 1 " "Info: 3: + IC(0.322 ns) + CELL(0.366 ns) = 5.764 ns; Loc. = LC_X52_Y1_N4; Fanout = 1; COMB Node = 'y~108'" {  } { { "d:/vhdl数字逻辑教程/5.1多路复用器#1/db/fuyongqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.1多路复用器#1/db/fuyongqi_cmp.qrpt" Compiler "fuyongqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.1多路复用器#1/db/fuyongqi.quartus_db" { Floorplan "" "" "0.688 ns" { y~107 y~108 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.1多路复用器#1/fuyongqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.1多路复用器#1/fuyongqi.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.114 ns) + CELL(2.404 ns) 9.282 ns y 4 PIN PIN_AA3 0 " "Info: 4: + IC(1.114 ns) + CELL(2.404 ns) = 9.282 ns; Loc. = PIN_AA3; Fanout = 0; PIN Node = 'y'" {  } { { "d:/vhdl数字逻辑教程/5.1多路复用器#1/db/fuyongqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.1多路复用器#1/db/fuyongqi_cmp.qrpt" Compiler "fuyongqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.1多路复用器#1/db/fuyongqi.quartus_db" { Floorplan "" "" "3.518 ns" { y~108 y } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.1多路复用器#1/fuyongqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.1多路复用器#1/fuyongqi.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.137 ns 44.57 % " "Info: Total cell delay = 4.137 ns ( 44.57 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.145 ns 55.43 % " "Info: Total interconnect delay = 5.145 ns ( 55.43 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/5.1多路复用器#1/db/fuyongqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.1多路复用器#1/db/fuyongqi_cmp.qrpt" Compiler "fuyongqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.1多路复用器#1/db/fuyongqi.quartus_db" { Floorplan "" "" "9.282 ns" { s0 y~107 y~108 y } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "a y 8.190 ns Shortest " "Info: Shortest tpd from source pin a to destination pin y is 8.190 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns a 1 PIN PIN_V4 1 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_V4; Fanout = 1; PIN Node = 'a'" {  } { { "d:/vhdl数字逻辑教程/5.1多路复用器#1/db/fuyongqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.1多路复用器#1/db/fuyongqi_cmp.qrpt" Compiler "fuyongqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.1多路复用器#1/db/fuyongqi.quartus_db" { Floorplan "" "" "" { a } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.1多路复用器#1/fuyongqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.1多路复用器#1/fuyongqi.vhd" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.158 ns) + CELL(0.280 ns) 4.672 ns y~108 2 COMB LC_X52_Y1_N4 1 " "Info: 2: + IC(3.158 ns) + CELL(0.280 ns) = 4.672 ns; Loc. = LC_X52_Y1_N4; Fanout = 1; COMB Node = 'y~108'" {  } { { "d:/vhdl数字逻辑教程/5.1多路复用器#1/db/fuyongqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.1多路复用器#1/db/fuyongqi_cmp.qrpt" Compiler "fuyongqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.1多路复用器#1/db/fuyongqi.quartus_db" { Floorplan "" "" "3.438 ns" { a y~108 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.1多路复用器#1/fuyongqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.1多路复用器#1/fuyongqi.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.114 ns) + CELL(2.404 ns) 8.190 ns y 3 PIN PIN_AA3 0 " "Info: 3: + IC(1.114 ns) + CELL(2.404 ns) = 8.190 ns; Loc. = PIN_AA3; Fanout = 0; PIN Node = 'y'" {  } { { "d:/vhdl数字逻辑教程/5.1多路复用器#1/db/fuyongqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.1多路复用器#1/db/fuyongqi_cmp.qrpt" Compiler "fuyongqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.1多路复用器#1/db/fuyongqi.quartus_db" { Floorplan "" "" "3.518 ns" { y~108 y } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.1多路复用器#1/fuyongqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.1多路复用器#1/fuyongqi.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.918 ns 47.84 % " "Info: Total cell delay = 3.918 ns ( 47.84 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.272 ns 52.16 % " "Info: Total interconnect delay = 4.272 ns ( 52.16 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/5.1多路复用器#1/db/fuyongqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.1多路复用器#1/db/fuyongqi_cmp.qrpt" Compiler "fuyongqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.1多路复用器#1/db/fuyongqi.quartus_db" { Floorplan "" "" "8.190 ns" { a y~108 y } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat May 12 16:20:28 2007 " "Info: Processing ended: Sat May 12 16:20:28 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}