yimaqi.tan.qmsg

是一些很好的FPGA设计实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 15 16:58:45 2007 " "Info: Processing started: Tue May 15 16:58:45 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off YIMAQI -c YIMAQI --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off YIMAQI -c YIMAQI --timing_analysis_only" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "x\[0\] y\[1\] 10.375 ns Longest " "Info: Longest tpd from source pin x\[0\] to destination pin y\[1\] is 10.375 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns x\[0\] 1 PIN PIN_Y5 5 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_Y5; Fanout = 5; PIN Node = 'x\[0\]'" {  } { { "d:/vhdl数字逻辑教程/5.4编码器/db/YIMAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.4编码器/db/YIMAQI_cmp.qrpt" Compiler "YIMAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.4编码器/db/YIMAQI.quartus_db" { Floorplan "" "" "" { x[0] } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.4编码器/YIMAQI.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.4编码器/YIMAQI.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.944 ns) + CELL(0.366 ns) 5.397 ns y~492 2 COMB LC_X50_Y1_N6 1 " "Info: 2: + IC(3.944 ns) + CELL(0.366 ns) = 5.397 ns; Loc. = LC_X50_Y1_N6; Fanout = 1; COMB Node = 'y~492'" {  } { { "d:/vhdl数字逻辑教程/5.4编码器/db/YIMAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.4编码器/db/YIMAQI_cmp.qrpt" Compiler "YIMAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.4编码器/db/YIMAQI.quartus_db" { Floorplan "" "" "4.310 ns" { x[0] y~492 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.4编码器/YIMAQI.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.4编码器/YIMAQI.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.488 ns) + CELL(0.075 ns) 5.960 ns y~490 3 COMB LC_X51_Y1_N4 1 " "Info: 3: + IC(0.488 ns) + CELL(0.075 ns) = 5.960 ns; Loc. = LC_X51_Y1_N4; Fanout = 1; COMB Node = 'y~490'" {  } { { "d:/vhdl数字逻辑教程/5.4编码器/db/YIMAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.4编码器/db/YIMAQI_cmp.qrpt" Compiler "YIMAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.4编码器/db/YIMAQI.quartus_db" { Floorplan "" "" "0.563 ns" { y~492 y~490 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.4编码器/YIMAQI.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.4编码器/YIMAQI.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.521 ns) + CELL(0.366 ns) 6.847 ns y~496 4 COMB LC_X50_Y1_N0 1 " "Info: 4: + IC(0.521 ns) + CELL(0.366 ns) = 6.847 ns; Loc. = LC_X50_Y1_N0; Fanout = 1; COMB Node = 'y~496'" {  } { { "d:/vhdl数字逻辑教程/5.4编码器/db/YIMAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.4编码器/db/YIMAQI_cmp.qrpt" Compiler "YIMAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.4编码器/db/YIMAQI.quartus_db" { Floorplan "" "" "0.887 ns" { y~490 y~496 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.4编码器/YIMAQI.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.4编码器/YIMAQI.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.124 ns) + CELL(2.404 ns) 10.375 ns y\[1\] 5 PIN PIN_AB4 0 " "Info: 5: + IC(1.124 ns) + CELL(2.404 ns) = 10.375 ns; Loc. = PIN_AB4; Fanout = 0; PIN Node = 'y\[1\]'" {  } { { "d:/vhdl数字逻辑教程/5.4编码器/db/YIMAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.4编码器/db/YIMAQI_cmp.qrpt" Compiler "YIMAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.4编码器/db/YIMAQI.quartus_db" { Floorplan "" "" "3.528 ns" { y~496 y[1] } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.4编码器/YIMAQI.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.4编码器/YIMAQI.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.298 ns 41.43 % " "Info: Total cell delay = 4.298 ns ( 41.43 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.077 ns 58.57 % " "Info: Total interconnect delay = 6.077 ns ( 58.57 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/5.4编码器/db/YIMAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.4编码器/db/YIMAQI_cmp.qrpt" Compiler "YIMAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.4编码器/db/YIMAQI.quartus_db" { Floorplan "" "" "10.375 ns" { x[0] y~492 y~490 y~496 y[1] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "x\[1\] y\[0\] 8.438 ns Shortest " "Info: Shortest tpd from source pin x\[1\] to destination pin y\[0\] is 8.438 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns x\[1\] 1 PIN PIN_AA4 5 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_AA4; Fanout = 5; PIN Node = 'x\[1\]'" {  } { { "d:/vhdl数字逻辑教程/5.4编码器/db/YIMAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.4编码器/db/YIMAQI_cmp.qrpt" Compiler "YIMAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.4编码器/db/YIMAQI.quartus_db" { Floorplan "" "" "" { x[1] } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.4编码器/YIMAQI.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.4编码器/YIMAQI.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.756 ns) + CELL(0.075 ns) 4.918 ns y~506 2 COMB LC_X50_Y1_N3 1 " "Info: 2: + IC(3.756 ns) + CELL(0.075 ns) = 4.918 ns; Loc. = LC_X50_Y1_N3; Fanout = 1; COMB Node = 'y~506'" {  } { { "d:/vhdl数字逻辑教程/5.4编码器/db/YIMAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.4编码器/db/YIMAQI_cmp.qrpt" Compiler "YIMAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.4编码器/db/YIMAQI.quartus_db" { Floorplan "" "" "3.831 ns" { x[1] y~506 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.4编码器/YIMAQI.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.4编码器/YIMAQI.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.116 ns) + CELL(2.404 ns) 8.438 ns y\[0\] 3 PIN PIN_Y2 0 " "Info: 3: + IC(1.116 ns) + CELL(2.404 ns) = 8.438 ns; Loc. = PIN_Y2; Fanout = 0; PIN Node = 'y\[0\]'" {  } { { "d:/vhdl数字逻辑教程/5.4编码器/db/YIMAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.4编码器/db/YIMAQI_cmp.qrpt" Compiler "YIMAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.4编码器/db/YIMAQI.quartus_db" { Floorplan "" "" "3.520 ns" { y~506 y[0] } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.4编码器/YIMAQI.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.4编码器/YIMAQI.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.566 ns 42.26 % " "Info: Total cell delay = 3.566 ns ( 42.26 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.872 ns 57.74 % " "Info: Total interconnect delay = 4.872 ns ( 57.74 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/5.4编码器/db/YIMAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.4编码器/db/YIMAQI_cmp.qrpt" Compiler "YIMAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.4编码器/db/YIMAQI.quartus_db" { Floorplan "" "" "8.438 ns" { x[1] y~506 y[0] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue May 15 16:58:46 2007 " "Info: Processing ended: Tue May 15 16:58:46 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}