yimaqi.hier_info

是一些很好的FPGA设计实例

|YIMAQI
x[0] => reduce_nor~0.IN6
x[0] => reduce_nor~1.IN6
x[0] => reduce_nor~2.IN6
x[0] => reduce_nor~3.IN6
x[0] => reduce_nor~4.IN6
x[0] => reduce_nor~5.IN6
x[0] => reduce_nor~6.IN6
x[0] => reduce_nor~7.IN6
x[1] => reduce_nor~0.IN5
x[1] => reduce_nor~1.IN5
x[1] => reduce_nor~2.IN5
x[1] => reduce_nor~3.IN5
x[1] => reduce_nor~4.IN5
x[1] => reduce_nor~5.IN5
x[1] => reduce_nor~7.IN5
x[1] => reduce_nor~6.IN5
x[2] => reduce_nor~0.IN4
x[2] => reduce_nor~1.IN4
x[2] => reduce_nor~2.IN4
x[2] => reduce_nor~3.IN4
x[2] => reduce_nor~4.IN4
x[2] => reduce_nor~6.IN4
x[2] => reduce_nor~7.IN4
x[2] => reduce_nor~5.IN4
x[3] => reduce_nor~0.IN7
x[3] => reduce_nor~1.IN7
x[3] => reduce_nor~2.IN7
x[3] => reduce_nor~3.IN7
x[3] => reduce_nor~5.IN7
x[3] => reduce_nor~6.IN7
x[3] => reduce_nor~7.IN7
x[3] => reduce_nor~4.IN7
x[4] => reduce_nor~0.IN3
x[4] => reduce_nor~1.IN3
x[4] => reduce_nor~2.IN3
x[4] => reduce_nor~4.IN3
x[4] => reduce_nor~5.IN3
x[4] => reduce_nor~6.IN3
x[4] => reduce_nor~7.IN3
x[4] => reduce_nor~3.IN3
x[5] => reduce_nor~0.IN2
x[5] => reduce_nor~1.IN2
x[5] => reduce_nor~3.IN2
x[5] => reduce_nor~4.IN2
x[5] => reduce_nor~5.IN2
x[5] => reduce_nor~6.IN2
x[5] => reduce_nor~7.IN2
x[5] => reduce_nor~2.IN2
x[6] => reduce_nor~0.IN1
x[6] => reduce_nor~2.IN1
x[6] => reduce_nor~3.IN1
x[6] => reduce_nor~4.IN1
x[6] => reduce_nor~5.IN1
x[6] => reduce_nor~6.IN1
x[6] => reduce_nor~7.IN1
x[6] => reduce_nor~1.IN1
x[7] => reduce_nor~1.IN0
x[7] => reduce_nor~2.IN0
x[7] => reduce_nor~3.IN0
x[7] => reduce_nor~4.IN0
x[7] => reduce_nor~5.IN0
x[7] => reduce_nor~6.IN0
x[7] => reduce_nor~7.IN0
x[7] => reduce_nor~0.IN0
y[0] <= y~26.DB_MAX_OUTPUT_PORT_TYPE
y[1] <= y~18.DB_MAX_OUTPUT_PORT_TYPE
y[2] <= y~11.DB_MAX_OUTPUT_PORT_TYPE