hcq.tan.qmsg

是一些很好的FPGA设计实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 18 19:06:34 2007 " "Info: Processing started: Fri May 18 19:06:34 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off hcq -c hcq --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off hcq -c hcq --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "ena output\[6\] 8.885 ns Longest " "Info: Longest tpd from source pin \"ena\" to destination pin \"output\[6\]\" is 8.885 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns ena 1 PIN PIN_W6 8 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_W6; Fanout = 8; PIN Node = 'ena'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ena } "NODE_NAME" } } { "hcq.vhd" "" { Text "H:/VHDL数字逻辑教程/5.3三态缓冲器/hcq.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.623 ns) + CELL(2.175 ns) 8.885 ns output\[6\] 2 PIN PIN_F6 0 " "Info: 2: + IC(5.623 ns) + CELL(2.175 ns) = 8.885 ns; Loc. = PIN_F6; Fanout = 0; PIN Node = 'output\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.798 ns" { ena output[6] } "NODE_NAME" } } { "hcq.vhd" "" { Text "H:/VHDL数字逻辑教程/5.3三态缓冲器/hcq.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.262 ns ( 36.71 % ) " "Info: Total cell delay = 3.262 ns ( 36.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.623 ns ( 63.29 % ) " "Info: Total interconnect delay = 5.623 ns ( 63.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.885 ns" { ena output[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.885 ns" { ena ena~out0 output[6] } { 0.000ns 0.000ns 5.623ns } { 0.000ns 1.087ns 2.175ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "input\[7\] output\[7\] 7.575 ns Shortest " "Info: Shortest tpd from source pin \"input\[7\]\" to destination pin \"output\[7\]\" is 7.575 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns input\[7\] 1 PIN PIN_A4 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_A4; Fanout = 1; PIN Node = 'input\[7\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { input[7] } "NODE_NAME" } } { "hcq.vhd" "" { Text "H:/VHDL数字逻辑教程/5.3三态缓冲器/hcq.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.084 ns) + CELL(2.404 ns) 7.575 ns output\[7\] 2 PIN PIN_C4 0 " "Info: 2: + IC(4.084 ns) + CELL(2.404 ns) = 7.575 ns; Loc. = PIN_C4; Fanout = 0; PIN Node = 'output\[7\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.488 ns" { input[7] output[7] } "NODE_NAME" } } { "hcq.vhd" "" { Text "H:/VHDL数字逻辑教程/5.3三态缓冲器/hcq.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.491 ns ( 46.09 % ) " "Info: Total cell delay = 3.491 ns ( 46.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.084 ns ( 53.91 % ) " "Info: Total interconnect delay = 4.084 ns ( 53.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.575 ns" { input[7] output[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.575 ns" { input[7] input[7]~out0 output[7] } { 0.000ns 0.000ns 4.084ns } { 0.000ns 1.087ns 2.404ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri May 18 19:06:38 2007 " "Info: Processing ended: Fri May 18 19:06:38 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}