cufaqi.tan.qmsg

是一些很好的FPGA设计实例

{ "Info" "ITDB_FULL_TCO_RESULT" "clk q q~reg0 6.539 ns register " "Info: tco from clock clk to destination pin q through register q~reg0 is 6.539 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.815 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 2.815 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns clk 1 CLK PIN_F14 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_F14; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" "" "" { Text "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.186 ns) + CELL(0.542 ns) 2.815 ns q~reg0 2 REG LC_X17_Y30_N2 1 " "Info: 2: + IC(1.186 ns) + CELL(0.542 ns) = 2.815 ns; Loc. = LC_X17_Y30_N2; Fanout = 1; REG Node = 'q~reg0'" {  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "1.728 ns" { clk q~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" "" "" { Text "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.629 ns 57.87 % " "Info: Total cell delay = 1.629 ns ( 57.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.186 ns 42.13 % " "Info: Total interconnect delay = 1.186 ns ( 42.13 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "2.815 ns" { clk q~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" "" "" { Text "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.568 ns + Longest register pin " "Info: + Longest register to pin delay is 3.568 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q~reg0 1 REG LC_X17_Y30_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y30_N2; Fanout = 1; REG Node = 'q~reg0'" {  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "" { q~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" "" "" { Text "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.164 ns) + CELL(2.404 ns) 3.568 ns q 2 PIN PIN_L16 0 " "Info: 2: + IC(1.164 ns) + CELL(2.404 ns) = 3.568 ns; Loc. = PIN_L16; Fanout = 0; PIN Node = 'q'" {  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "3.568 ns" { q~reg0 q } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" "" "" { Text "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns 67.38 % " "Info: Total cell delay = 2.404 ns ( 67.38 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.164 ns 32.62 % " "Info: Total interconnect delay = 1.164 ns ( 32.62 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "3.568 ns" { q~reg0 q } "NODE_NAME" } } }  } 0}  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "2.815 ns" { clk q~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "3.568 ns" { q~reg0 q } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "q~reg0 d clk -1.942 ns register " "Info: th for register q~reg0 (data pin = d, clock pin = clk) is -1.942 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.815 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 2.815 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns clk 1 CLK PIN_F14 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_F14; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" "" "" { Text "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.186 ns) + CELL(0.542 ns) 2.815 ns q~reg0 2 REG LC_X17_Y30_N2 1 " "Info: 2: + IC(1.186 ns) + CELL(0.542 ns) = 2.815 ns; Loc. = LC_X17_Y30_N2; Fanout = 1; REG Node = 'q~reg0'" {  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "1.728 ns" { clk q~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" "" "" { Text "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.629 ns 57.87 % " "Info: Total cell delay = 1.629 ns ( 57.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.186 ns 42.13 % " "Info: Total interconnect delay = 1.186 ns ( 42.13 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "2.815 ns" { clk q~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" "" "" { Text "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.857 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.857 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns d 1 PIN PIN_J15 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_J15; Fanout = 1; PIN Node = 'd'" {  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "" { d } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" "" "" { Text "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.685 ns) + CELL(0.085 ns) 4.857 ns q~reg0 2 REG LC_X17_Y30_N2 1 " "Info: 2: + IC(3.685 ns) + CELL(0.085 ns) = 4.857 ns; Loc. = LC_X17_Y30_N2; Fanout = 1; REG Node = 'q~reg0'" {  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "3.770 ns" { d q~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" "" "" { Text "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.172 ns 24.13 % " "Info: Total cell delay = 1.172 ns ( 24.13 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.685 ns 75.87 % " "Info: Total interconnect delay = 3.685 ns ( 75.87 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "4.857 ns" { d q~reg0 } "NODE_NAME" } } }  } 0}  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "2.815 ns" { clk q~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "4.857 ns" { d q~reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk q q~reg0 6.539 ns register " "Info: Minimum tco from clock clk to destination pin q through register q~reg0 is 6.539 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.815 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 2.815 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns clk 1 CLK PIN_F14 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_F14; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" "" "" { Text "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.186 ns) + CELL(0.542 ns) 2.815 ns q~reg0 2 REG LC_X17_Y30_N2 1 " "Info: 2: + IC(1.186 ns) + CELL(0.542 ns) = 2.815 ns; Loc. = LC_X17_Y30_N2; Fanout = 1; REG Node = 'q~reg0'" {  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "1.728 ns" { clk q~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" "" "" { Text "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.629 ns 57.87 % " "Info: Total cell delay = 1.629 ns ( 57.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.186 ns 42.13 % " "Info: Total interconnect delay = 1.186 ns ( 42.13 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "2.815 ns" { clk q~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" "" "" { Text "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.568 ns + Shortest register pin " "Info: + Shortest register to pin delay is 3.568 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q~reg0 1 REG LC_X17_Y30_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y30_N2; Fanout = 1; REG Node = 'q~reg0'" {  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "" { q~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" "" "" { Text "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.164 ns) + CELL(2.404 ns) 3.568 ns q 2 PIN PIN_L16 0 " "Info: 2: + IC(1.164 ns) + CELL(2.404 ns) = 3.568 ns; Loc. = PIN_L16; Fanout = 0; PIN Node = 'q'" {  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "3.568 ns" { q~reg0 q } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" "" "" { Text "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns 67.38 % " "Info: Total cell delay = 2.404 ns ( 67.38 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.164 ns 32.62 % " "Info: Total interconnect delay = 1.164 ns ( 32.62 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "3.568 ns" { q~reg0 q } "NODE_NAME" } } }  } 0}  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "2.815 ns" { clk q~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "3.568 ns" { q~reg0 q } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat May 12 15:19:45 2007 " "Info: Processing ended: Sat May 12 15:19:45 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}