cufaqi.tan.qmsg

是一些很好的FPGA设计实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 12 15:19:44 2007 " "Info: Processing started: Sat May 12 15:19:44 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off CUFAQI -c CUFAQI --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off CUFAQI -c CUFAQI --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" "" "" { Text "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" 4 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk " "Info: No valid register-to-register paths exist for clock clk" {  } {  } 0}
{ "Info" "ITDB_TSU_RESULT" "q~reg0 d clk 2.052 ns register " "Info: tsu for register q~reg0 (data pin = d, clock pin = clk) is 2.052 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.857 ns + Longest pin register " "Info: + Longest pin to register delay is 4.857 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns d 1 PIN PIN_J15 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_J15; Fanout = 1; PIN Node = 'd'" {  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "" { d } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" "" "" { Text "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.685 ns) + CELL(0.085 ns) 4.857 ns q~reg0 2 REG LC_X17_Y30_N2 1 " "Info: 2: + IC(3.685 ns) + CELL(0.085 ns) = 4.857 ns; Loc. = LC_X17_Y30_N2; Fanout = 1; REG Node = 'q~reg0'" {  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "3.770 ns" { d q~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" "" "" { Text "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.172 ns 24.13 % " "Info: Total cell delay = 1.172 ns ( 24.13 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.685 ns 75.87 % " "Info: Total interconnect delay = 3.685 ns ( 75.87 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "4.857 ns" { d q~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" "" "" { Text "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.815 ns - Shortest register " "Info: - Shortest clock path from clock clk to destination register is 2.815 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns clk 1 CLK PIN_F14 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_F14; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" "" "" { Text "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.186 ns) + CELL(0.542 ns) 2.815 ns q~reg0 2 REG LC_X17_Y30_N2 1 " "Info: 2: + IC(1.186 ns) + CELL(0.542 ns) = 2.815 ns; Loc. = LC_X17_Y30_N2; Fanout = 1; REG Node = 'q~reg0'" {  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "1.728 ns" { clk q~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" "" "" { Text "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.629 ns 57.87 % " "Info: Total cell delay = 1.629 ns ( 57.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.186 ns 42.13 % " "Info: Total interconnect delay = 1.186 ns ( 42.13 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "2.815 ns" { clk q~reg0 } "NODE_NAME" } } }  } 0}  } { { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "4.857 ns" { d q~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI_cmp.qrpt" Compiler "CUFAQI" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/db/CUFAQI.quartus_db" { Floorplan "" "" "2.815 ns" { clk q~reg0 } "NODE_NAME" } } }  } 0}