fuyongqi.map.qmsg

是一些很好的FPGA设计实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 15 16:31:50 2007 " "Info: Processing started: Tue May 15 16:31:50 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off fuyongqi -c fuyongqi " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off fuyongqi -c fuyongqi" {  } {  } 0}
{ "Error" "EVRFX_VHDL_OVERWRITING_PRIMARY_UNIT" "fuyongqi.vhd(20) " "Error: VHDL Entity Declaration warning at fuyongqi.vhd(20): primary unit already exists -- overwriting existing primary unit with new primary unit" {  } { { "d:/vhdl数字逻辑教程/5.2多路复用器#2/fuyongqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.2多路复用器#2/fuyongqi.vhd" 20 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_OVERWRITING_PRIMARY_UNIT" "fuyongqi.vhd(41) " "Error: VHDL Entity Declaration warning at fuyongqi.vhd(41): primary unit already exists -- overwriting existing primary unit with new primary unit" {  } { { "d:/vhdl数字逻辑教程/5.2多路复用器#2/fuyongqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.2多路复用器#2/fuyongqi.vhd" 41 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fuyongqi.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file fuyongqi.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fuyongqi-fuyongqi1 " "Info: Found design unit 1: fuyongqi-fuyongqi1" {  } { { "d:/vhdl数字逻辑教程/5.2多路复用器#2/fuyongqi.vhd" "fuyongqi-fuyongqi1" "" { Text "d:/vhdl数字逻辑教程/5.2多路复用器#2/fuyongqi.vhd" 47 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 fuyongqi-fuyongqi2 " "Info: Found design unit 2: fuyongqi-fuyongqi2" {  } { { "d:/vhdl数字逻辑教程/5.2多路复用器#2/fuyongqi.vhd" "fuyongqi-fuyongqi2" "" { Text "d:/vhdl数字逻辑教程/5.2多路复用器#2/fuyongqi.vhd" 55 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 fuyongqi " "Info: Found entity 1: fuyongqi" {  } { { "d:/vhdl数字逻辑教程/5.2多路复用器#2/fuyongqi.vhd" "fuyongqi" "" { Text "d:/vhdl数字逻辑教程/5.2多路复用器#2/fuyongqi.vhd" 41 -1 0 } }  } 0}  } {  } 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 0 s " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Tue May 15 16:31:53 2007 " "Error: Processing ended: Tue May 15 16:31:53 2007" {  } {  } 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}