yimaqi.tan.qmsg

是一些很好的FPGA设计实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 14 17:04:15 2007 " "Info: Processing started: Mon May 14 17:04:15 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off yimaqi -c yimaqi --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off yimaqi -c yimaqi --timing_analysis_only" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "sel\[1\] x\[1\] 9.021 ns Longest " "Info: Longest tpd from source pin sel\[1\] to destination pin x\[1\] is 9.021 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns sel\[1\] 1 PIN PIN_AB17 8 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_AB17; Fanout = 8; PIN Node = 'sel\[1\]'" {  } { { "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" Compiler "yimaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi.quartus_db" { Floorplan "" "" "" { sel[1] } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.823 ns) + CELL(0.366 ns) 5.276 ns temp1~14 2 COMB LC_X5_Y1_N5 1 " "Info: 2: + IC(3.823 ns) + CELL(0.366 ns) = 5.276 ns; Loc. = LC_X5_Y1_N5; Fanout = 1; COMB Node = 'temp1~14'" {  } { { "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" Compiler "yimaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi.quartus_db" { Floorplan "" "" "4.189 ns" { sel[1] temp1~14 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.341 ns) + CELL(2.404 ns) 9.021 ns x\[1\] 3 PIN PIN_Y19 0 " "Info: 3: + IC(1.341 ns) + CELL(2.404 ns) = 9.021 ns; Loc. = PIN_Y19; Fanout = 0; PIN Node = 'x\[1\]'" {  } { { "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" Compiler "yimaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi.quartus_db" { Floorplan "" "" "3.745 ns" { temp1~14 x[1] } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.857 ns 42.76 % " "Info: Total cell delay = 3.857 ns ( 42.76 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.164 ns 57.24 % " "Info: Total interconnect delay = 5.164 ns ( 57.24 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" Compiler "yimaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi.quartus_db" { Floorplan "" "" "9.021 ns" { sel[1] temp1~14 x[1] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "sel\[2\] x\[5\] 8.483 ns Shortest " "Info: Shortest tpd from source pin sel\[2\] to destination pin x\[5\] is 8.483 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns sel\[2\] 1 PIN PIN_W17 8 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_W17; Fanout = 8; PIN Node = 'sel\[2\]'" {  } { { "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" Compiler "yimaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi.quartus_db" { Floorplan "" "" "" { sel[2] } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.801 ns) + CELL(0.075 ns) 4.963 ns temp1~10 2 COMB LC_X5_Y1_N7 1 " "Info: 2: + IC(3.801 ns) + CELL(0.075 ns) = 4.963 ns; Loc. = LC_X5_Y1_N7; Fanout = 1; COMB Node = 'temp1~10'" {  } { { "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" Compiler "yimaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi.quartus_db" { Floorplan "" "" "3.876 ns" { sel[2] temp1~10 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.116 ns) + CELL(2.404 ns) 8.483 ns x\[5\] 3 PIN PIN_V18 0 " "Info: 3: + IC(1.116 ns) + CELL(2.404 ns) = 8.483 ns; Loc. = PIN_V18; Fanout = 0; PIN Node = 'x\[5\]'" {  } { { "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" Compiler "yimaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi.quartus_db" { Floorplan "" "" "3.520 ns" { temp1~10 x[5] } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.566 ns 42.04 % " "Info: Total cell delay = 3.566 ns ( 42.04 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.917 ns 57.96 % " "Info: Total interconnect delay = 4.917 ns ( 57.96 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" Compiler "yimaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi.quartus_db" { Floorplan "" "" "8.483 ns" { sel[2] temp1~10 x[5] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon May 14 17:04:16 2007 " "Info: Processing ended: Mon May 14 17:04:16 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}