simple_fsm.tan.qmsg

是一些很好的FPGA设计实例

{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk x x~reg0 6.098 ns register " "Info: Minimum tco from clock clk to destination pin x through register x~reg0 is 6.098 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.772 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 2.772 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.505 ns) + CELL(0.542 ns) 2.772 ns x~reg0 2 REG LC_X52_Y30_N4 1 " "Info: 2: + IC(1.505 ns) + CELL(0.542 ns) = 2.772 ns; Loc. = LC_X52_Y30_N4; Fanout = 1; REG Node = 'x~reg0'" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "2.047 ns" { clk x~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 45.71 % " "Info: Total cell delay = 1.267 ns ( 45.71 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.505 ns 54.29 % " "Info: Total interconnect delay = 1.505 ns ( 54.29 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "2.772 ns" { clk x~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.170 ns + Shortest register pin " "Info: + Shortest register to pin delay is 3.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns x~reg0 1 REG LC_X52_Y30_N4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y30_N4; Fanout = 1; REG Node = 'x~reg0'" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "" { x~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.794 ns) + CELL(2.376 ns) 3.170 ns x 2 PIN PIN_D2 0 " "Info: 2: + IC(0.794 ns) + CELL(2.376 ns) = 3.170 ns; Loc. = PIN_D2; Fanout = 0; PIN Node = 'x'" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "3.170 ns" { x~reg0 x } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.376 ns 74.95 % " "Info: Total cell delay = 2.376 ns ( 74.95 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.794 ns 25.05 % " "Info: Total interconnect delay = 0.794 ns ( 25.05 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "3.170 ns" { x~reg0 x } "NODE_NAME" } } }  } 0}  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "2.772 ns" { clk x~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "3.170 ns" { x~reg0 x } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu May 17 11:55:44 2007 " "Info: Processing ended: Thu May 17 11:55:44 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}