simple_fsm.fit.qmsg

是一些很好的FPGA设计实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 17 11:54:03 2007 " "Info: Processing started: Thu May 17 11:54:03 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off simple_fsm -c simple_fsm " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off simple_fsm -c simple_fsm" {  } {  } 0}
{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "simple_fsm EP1S10F484C5 " "Info: Automatically selected device EP1S10F484C5 for design simple_fsm" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation -- Fitter effort may be decreased to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S20F484C5 " "Info: Device EP1S20F484C5 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "6 6 " "Info: No exact pin location assignment(s) for 6 pins of 6 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "x " "Info: Pin x not assigned to an exact location on the device" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 6 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "x" } } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "" { x } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.fld" "" "" { Floorplan "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.fld" "" "" { x } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b " "Info: Pin b not assigned to an exact location on the device" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 5 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "b" } } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "" { b } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.fld" "" "" { Floorplan "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.fld" "" "" { b } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a " "Info: Pin a not assigned to an exact location on the device" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 5 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "a" } } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "" { a } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.fld" "" "" { Floorplan "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.fld" "" "" { a } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "clk " "Info: Pin clk not assigned to an exact location on the device" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 5 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.fld" "" "" { Floorplan "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.fld" "" "" { clk } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "rst " "Info: Pin rst not assigned to an exact location on the device" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 5 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "rst" } } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "" { rst } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.fld" "" "" { Floorplan "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.fld" "" "" { rst } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d " "Info: Pin d not assigned to an exact location on the device" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 5 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "d" } } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "" { d } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.fld" "" "" { Floorplan "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.fld" "" "" { d } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN L2 " "Info: Automatically promoted signal clk to use Global clock in PIN L2" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 5 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_START_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Start DSP scan-chain inferencing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Completed DSP scan-chain inferencing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_START_LUT_IO_MAC_RAM_PACKING" "" "Info: Moving registers into I/Os, LUTs, DSP and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFYGR_FYGR_FINISH_LUT_IO_MAC_RAM_PACKING" "" "Info: Finished moving registers into I/Os, LUTs, DSP and RAM blocks" {  } {  } 0}