jishuqi.map.qmsg

是一些很好的FPGA设计实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 17 10:48:44 2007 " "Info: Processing started: Thu May 17 10:48:44 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off jishuqi -c jishuqi " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off jishuqi -c jishuqi" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jishuqi.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file jishuqi.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 jishuqi-jishuqi " "Info: Found design unit 1: jishuqi-jishuqi" {  } { { "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" "jishuqi-jishuqi" "" { Text "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" 10 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 jishuqi " "Info: Found entity 1: jishuqi" {  } { { "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" "jishuqi" "" { Text "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISMP_SMP_MACHINE_PREPROCESS_STAT" "\|jishuqi\|pr_state 10 0 " "Info: State machine \|jishuqi\|pr_state contains 10 states and 0 state bits" {  } {  } 0}
{ "Info" "ISMP_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|jishuqi\|pr_state " "Info: Selected Auto state machine encoding method for state machine \|jishuqi\|pr_state" {  } {  } 0}
{ "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|jishuqi\|pr_state " "Info: Encoding result for state machine \|jishuqi\|pr_state" { { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "10 " "Info: Completed encoding using 10 state bits" { { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "pr_state~29 " "Info: Encoded state bit pr_state~29" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "pr_state~28 " "Info: Encoded state bit pr_state~28" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "pr_state~27 " "Info: Encoded state bit pr_state~27" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "pr_state~26 " "Info: Encoded state bit pr_state~26" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "pr_state~25 " "Info: Encoded state bit pr_state~25" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "pr_state~24 " "Info: Encoded state bit pr_state~24" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "pr_state~23 " "Info: Encoded state bit pr_state~23" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "pr_state~22 " "Info: Encoded state bit pr_state~22" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "pr_state~21 " "Info: Encoded state bit pr_state~21" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "pr_state~20 " "Info: Encoded state bit pr_state~20" {  } {  } 0}  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|jishuqi\|pr_state.zero 0000000000 " "Info: State \|jishuqi\|pr_state.zero uses code string 0000000000" {  } { { "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" 12 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|jishuqi\|pr_state.one 0000000011 " "Info: State \|jishuqi\|pr_state.one uses code string 0000000011" {  } { { "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" 12 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|jishuqi\|pr_state.two 0000000101 " "Info: State \|jishuqi\|pr_state.two uses code string 0000000101" {  } { { "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" 12 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|jishuqi\|pr_state.three 0000001001 " "Info: State \|jishuqi\|pr_state.three uses code string 0000001001" {  } { { "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" 12 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|jishuqi\|pr_state.four 0000010001 " "Info: State \|jishuqi\|pr_state.four uses code string 0000010001" {  } { { "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" 12 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|jishuqi\|pr_state.five 0000100001 " "Info: State \|jishuqi\|pr_state.five uses code string 0000100001" {  } { { "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" 12 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|jishuqi\|pr_state.six 0001000001 " "Info: State \|jishuqi\|pr_state.six uses code string 0001000001" {  } { { "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" 12 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|jishuqi\|pr_state.seven 0010000001 " "Info: State \|jishuqi\|pr_state.seven uses code string 0010000001" {  } { { "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" 12 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|jishuqi\|pr_state.eight 0100000001 " "Info: State \|jishuqi\|pr_state.eight uses code string 0100000001" {  } { { "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" 12 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|jishuqi\|pr_state.nine 1000000001 " "Info: State \|jishuqi\|pr_state.nine uses code string 1000000001" {  } { { "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" 12 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "21 " "Info: Implemented 21 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "4 " "Info: Implemented 4 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "15 " "Info: Implemented 15 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu May 17 10:48:49 2007 " "Info: Processing ended: Thu May 17 10:48:49 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}