jishuqi.tan.qmsg

是一些很好的FPGA设计实例

{ "Info" "ITDB_FULL_TCO_RESULT" "clk count\[0\] pr_state~24 7.969 ns register " "Info: tco from clock clk to destination pin count\[0\] through register pr_state~24 is 7.969 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.835 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 2.835 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 10 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 10; CLK Node = 'clk'" {  } { { "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.568 ns) + CELL(0.542 ns) 2.835 ns pr_state~24 2 REG LC_X1_Y30_N0 3 " "Info: 2: + IC(1.568 ns) + CELL(0.542 ns) = 2.835 ns; Loc. = LC_X1_Y30_N0; Fanout = 3; REG Node = 'pr_state~24'" {  } { { "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi.quartus_db" { Floorplan "" "" "2.110 ns" { clk pr_state~24 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 44.69 % " "Info: Total cell delay = 1.267 ns ( 44.69 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.568 ns 55.31 % " "Info: Total interconnect delay = 1.568 ns ( 55.31 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi.quartus_db" { Floorplan "" "" "2.835 ns" { clk pr_state~24 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.978 ns + Longest register pin " "Info: + Longest register to pin delay is 4.978 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pr_state~24 1 REG LC_X1_Y30_N0 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y30_N0; Fanout = 3; REG Node = 'pr_state~24'" {  } { { "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi.quartus_db" { Floorplan "" "" "" { pr_state~24 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.532 ns) + CELL(0.366 ns) 0.898 ns reduce_or~51 2 COMB LC_X2_Y30_N2 1 " "Info: 2: + IC(0.532 ns) + CELL(0.366 ns) = 0.898 ns; Loc. = LC_X2_Y30_N2; Fanout = 1; COMB Node = 'reduce_or~51'" {  } { { "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi.quartus_db" { Floorplan "" "" "0.898 ns" { pr_state~24 reduce_or~51 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.482 ns) + CELL(0.075 ns) 1.455 ns reduce_or~2 3 COMB LC_X1_Y30_N7 1 " "Info: 3: + IC(0.482 ns) + CELL(0.075 ns) = 1.455 ns; Loc. = LC_X1_Y30_N7; Fanout = 1; COMB Node = 'reduce_or~2'" {  } { { "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi.quartus_db" { Floorplan "" "" "0.557 ns" { reduce_or~51 reduce_or~2 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.119 ns) + CELL(2.404 ns) 4.978 ns count\[0\] 4 PIN PIN_B20 0 " "Info: 4: + IC(1.119 ns) + CELL(2.404 ns) = 4.978 ns; Loc. = PIN_B20; Fanout = 0; PIN Node = 'count\[0\]'" {  } { { "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi.quartus_db" { Floorplan "" "" "3.523 ns" { reduce_or~2 count[0] } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.845 ns 57.15 % " "Info: Total cell delay = 2.845 ns ( 57.15 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.133 ns 42.85 % " "Info: Total interconnect delay = 2.133 ns ( 42.85 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi.quartus_db" { Floorplan "" "" "4.978 ns" { pr_state~24 reduce_or~51 reduce_or~2 count[0] } "NODE_NAME" } } }  } 0}  } { { "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi.quartus_db" { Floorplan "" "" "2.835 ns" { clk pr_state~24 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi.quartus_db" { Floorplan "" "" "4.978 ns" { pr_state~24 reduce_or~51 reduce_or~2 count[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk count\[3\] pr_state~28 6.349 ns register " "Info: Minimum tco from clock clk to destination pin count\[3\] through register pr_state~28 is 6.349 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.835 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 2.835 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 10 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 10; CLK Node = 'clk'" {  } { { "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.568 ns) + CELL(0.542 ns) 2.835 ns pr_state~28 2 REG LC_X1_Y30_N4 3 " "Info: 2: + IC(1.568 ns) + CELL(0.542 ns) = 2.835 ns; Loc. = LC_X1_Y30_N4; Fanout = 3; REG Node = 'pr_state~28'" {  } { { "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi.quartus_db" { Floorplan "" "" "2.110 ns" { clk pr_state~28 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 44.69 % " "Info: Total cell delay = 1.267 ns ( 44.69 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.568 ns 55.31 % " "Info: Total interconnect delay = 1.568 ns ( 55.31 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi.quartus_db" { Floorplan "" "" "2.835 ns" { clk pr_state~28 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.358 ns + Shortest register pin " "Info: + Shortest register to pin delay is 3.358 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pr_state~28 1 REG LC_X1_Y30_N4 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y30_N4; Fanout = 3; REG Node = 'pr_state~28'" {  } { { "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi.quartus_db" { Floorplan "" "" "" { pr_state~28 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.230 ns) 0.230 ns count~0 2 COMB LC_X1_Y30_N4 1 " "Info: 2: + IC(0.000 ns) + CELL(0.230 ns) = 0.230 ns; Loc. = LC_X1_Y30_N4; Fanout = 1; COMB Node = 'count~0'" {  } { { "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi.quartus_db" { Floorplan "" "" "0.230 ns" { pr_state~28 count~0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.752 ns) + CELL(2.376 ns) 3.358 ns count\[3\] 3 PIN PIN_E19 0 " "Info: 3: + IC(0.752 ns) + CELL(2.376 ns) = 3.358 ns; Loc. = PIN_E19; Fanout = 0; PIN Node = 'count\[3\]'" {  } { { "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi.quartus_db" { Floorplan "" "" "3.128 ns" { count~0 count[3] } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.606 ns 77.61 % " "Info: Total cell delay = 2.606 ns ( 77.61 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.752 ns 22.39 % " "Info: Total interconnect delay = 0.752 ns ( 22.39 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi.quartus_db" { Floorplan "" "" "3.358 ns" { pr_state~28 count~0 count[3] } "NODE_NAME" } } }  } 0}  } { { "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi.quartus_db" { Floorplan "" "" "2.835 ns" { clk pr_state~28 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.1bcd计数器/db/jishuqi.quartus_db" { Floorplan "" "" "3.358 ns" { pr_state~28 count~0 count[3] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu May 17 10:50:56 2007 " "Info: Processing ended: Thu May 17 10:50:56 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}