yiweijcq.map.qmsg

来自「是一些很好的FPGA设计实例」· QMSG 代码 · 共 7 行

QMSG
7
字号
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 16 16:56:12 2007 " "Info: Processing started: Wed May 16 16:56:12 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off yiweijcq -c yiweijcq " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off yiweijcq -c yiweijcq" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yiweijcq.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file yiweijcq.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 yiweijcq-yiweijcq " "Info: Found design unit 1: yiweijcq-yiweijcq" {  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "yiweijcq-yiweijcq" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 7 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 yiweijcq " "Info: Found entity 1: yiweijcq" {  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "yiweijcq" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 2 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "7 " "Info: Implemented 7 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "4 " "Info: Implemented 4 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed May 16 16:56:16 2007 " "Info: Processing ended: Wed May 16 16:56:16 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}

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