yiweijcq.tan.qmsg

是一些很好的FPGA设计实例

{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk dout dout~reg0 6.200 ns register " "Info: Minimum tco from clock clk to destination pin dout through register dout~reg0 is 6.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.500 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clk 1 CLK PIN_39 4 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns dout~reg0 2 REG LC2_C4 1 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC2_C4; Fanout = 1; REG Node = 'dout~reg0'" {  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "0.200 ns" { clk dout~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 86.67 % " "Info: Total cell delay = 1.300 ns ( 86.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 13.33 % " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "1.500 ns" { clk dout~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.300 ns + " "Info: + Micro clock to output delay of source is 0.300 ns" {  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.400 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dout~reg0 1 REG LC2_C4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_C4; Fanout = 1; REG Node = 'dout~reg0'" {  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "" { dout~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(3.800 ns) 4.400 ns dout 2 PIN PIN_57 0 " "Info: 2: + IC(0.600 ns) + CELL(3.800 ns) = 4.400 ns; Loc. = PIN_57; Fanout = 0; PIN Node = 'dout'" {  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "4.400 ns" { dout~reg0 dout } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.800 ns 86.36 % " "Info: Total cell delay = 3.800 ns ( 86.36 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns 13.64 % " "Info: Total interconnect delay = 0.600 ns ( 13.64 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "4.400 ns" { dout~reg0 dout } "NODE_NAME" } } }  } 0}  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "1.500 ns" { clk dout~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "4.400 ns" { dout~reg0 dout } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed May 16 16:56:29 2007 " "Info: Processing ended: Wed May 16 16:56:29 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}